LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	19.090s	491.111us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	29.366us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	17.522us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.170s	52.920us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.440s	18.008us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.930s	31.417us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	17.522us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	18.008us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.940s	158.029us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.550s	1.635ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	10.779us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.860s	177.535us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.790s	619.898us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_prog_failure	6.860s	177.535us	50	50	100.00
		lc_ctrl_errors	25.790s	619.898us	50	50	100.00
		lc_ctrl_security_escalation	16.840s	3.785ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.609m	2.836ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.300s	1.090ms	20	20	100.00
		lc_ctrl_jtag_errors	2.424m	90.825ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.030s	758.768us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.770s	3.387ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.300s	1.090ms	20	20	100.00
		lc_ctrl_jtag_errors	2.424m	90.825ms	20	20	100.00
		lc_ctrl_jtag_access	22.720s	4.147ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.510s	2.466ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.200s	214.289us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.330s	774.233us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	54.390s	14.683ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.350s	1.243ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.160s	60.075us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.410s	3.283ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.840s	399.793us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	27.530s	2.323ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.290s	16.611us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	12.485m	48.803ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	37.003us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.100s	121.394us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.100s	121.394us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	29.366us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	17.522us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	18.008us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	97.486us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	29.366us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	17.522us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	18.008us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	97.486us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
		lc_ctrl_tl_intg_err	4.220s	290.941us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.220s	290.941us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.550s	1.635ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.650s	1.069ms	50	50	100.00
		lc_ctrl_sec_cm	28.860s	661.833us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.840s	3.785ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.940s	158.029us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.770s	3.387ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.180s	1.621ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.180s	1.621ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.640s	2.358ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.070s	594.979us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.070s	594.979us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.772h	113.852ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.63	97.99	96.04	93.38	95.35	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.74483569631088998399022908148450323297715441566295639357140735090499141712232
      Line 10882, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5430051314 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5430051314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.51164789504172099656210226382558131806623352220986496424884269567547584750229
      Line 6754, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8538229045 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8538229045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.40145345006697496759712648382594232475026989809958642777093201868801572723143
      Line 8462, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3518608749 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 3518608749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.lc_ctrl_stress_all_with_rand_reset.113736937410479161955697162238364309033728351023946216835236439297247205757950
      Line 43772, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 80458214119 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 80458214119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.68977334775619775843914730895312548950359216105867642498386698741577761785024
      Line 33397, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 5.lc_ctrl_jtag_priority.48951487429062973121130018462181275761532351895992876667054148721838846244527
      Line 460, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10012675274 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10012675274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.98686059595431638925661236659943147789526356548992873039350056563562626599697
      Line 27077, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63190179031 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 63190179031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 7.lc_ctrl_volatile_unlock_smoke.85798462640293481913735554990152853892277004503865839044650007739483686138390
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 154431287 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x4f3a8f04) == 0x1
        UVM_INFO @ 154431287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.82535815669033946625733721035401228548485752097625903567620172632927856618881
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:f3303bc1-ee78-4874-9c3c-b0fbfe44c119
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.66557674880325544926064022895143097511022941845710491378998270801765810024018
      Line 8662, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27662482041 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 27662482041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.06.23_07.50.28
• 2024.06.22_11.35.08
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