LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.180s	1.330ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.270s	66.937us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	55.782us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.040s	104.431us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.710s	32.328us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.160s	123.169us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	55.782us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	32.328us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.140s	227.112us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.140s	1.434ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	12.596us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.490s	360.575us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.830s	1.766ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_prog_failure	4.490s	360.575us	50	50	100.00
		lc_ctrl_errors	23.830s	1.766ms	50	50	100.00
		lc_ctrl_security_escalation	16.300s	394.044us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.109m	3.975ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.860s	613.810us	20	20	100.00
		lc_ctrl_jtag_errors	1.238m	35.683ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.390s	379.512us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.210s	864.194us	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.860s	613.810us	20	20	100.00
		lc_ctrl_jtag_errors	1.238m	35.683ms	20	20	100.00
		lc_ctrl_jtag_access	17.800s	816.857us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.900s	5.577ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.960s	398.616us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.010s	241.303us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	56.390s	3.428ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.100s	2.746ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.780s	143.138us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.250s	102.022us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.170s	360.618us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	7.480s	279.729us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	31.983us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.642m	27.797ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	29.194us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.380s	342.836us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.380s	342.836us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.270s	66.937us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	55.782us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	32.328us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	94.302us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.270s	66.937us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	55.782us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	32.328us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	94.302us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
		lc_ctrl_tl_intg_err	3.840s	364.402us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.840s	364.402us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.140s	1.434ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.380s	1.945ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	341.373us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.300s	394.044us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.140s	227.112us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.210s	864.194us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.100s	572.542us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.100s	572.542us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.360s	1.024ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.560s	2.726ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.560s	2.726ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.255h	283.945ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.99	95.50	93.38	97.67	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.115373383564786595306188372039834994500420554275075395951974329083168205388120
      Line 30749, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55550949456 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 55550949456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.78385397214753235265256736865125629032340640539750781288139257074558435334532
      Line 437, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2103196484 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2103196484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.13097415072975480291874445900644420945285139647875976307953948678273398722797
      Line 14875, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 308909538478 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 308909538478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.67831669729708036356266846249433772975232159590804788964408059682488278091313
      Line 32505, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 110774903814 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 110774903814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.3061173372610212025017413701344257827822799920814442251099495119459284789628
      Line 44238, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.06.26_11.09.35
• 2024.06.25_11.32.22
• 2024.06.24_08.29.34
• 2024.06.23_07.50.28
• 2024.06.22_11.35.08
• 2024.06.14_07.14.50
• 2024.06.12_04.50.28