LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.450s	108.399us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	159.616us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	16.940us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.750s	100.852us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.800s	73.042us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.770s	23.105us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	16.940us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	73.042us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.380s	195.787us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.550s	409.797us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	42.521us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.340s	192.718us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.420s	1.122ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_prog_failure	4.340s	192.718us	50	50	100.00
		lc_ctrl_errors	24.420s	1.122ms	50	50	100.00
		lc_ctrl_security_escalation	14.550s	2.522ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.555m	6.130ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.420s	3.192ms	20	20	100.00
		lc_ctrl_jtag_errors	2.092m	39.531ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.740s	1.306ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	20.200s	2.837ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.420s	3.192ms	20	20	100.00
		lc_ctrl_jtag_errors	2.092m	39.531ms	20	20	100.00
		lc_ctrl_jtag_access	31.110s	1.390ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.470s	1.375ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.720s	1.812ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.550s	367.202us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	20.820s	981.089us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.490s	1.885ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.780s	168.659us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.440s	950.934us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.700s	137.973us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.870s	2.575ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	17.985us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.403m	136.892ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.340s	23.716us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.200s	481.581us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.200s	481.581us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	159.616us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	16.940us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	73.042us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	55.656us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	159.616us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	16.940us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	73.042us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	55.656us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.440s	130.997us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.440s	130.997us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.550s	409.797us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.970s	331.912us	50	50	100.00
		lc_ctrl_sec_cm	45.990s	1.734ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.550s	2.522ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.380s	195.787us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	20.200s	2.837ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.660s	671.044us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.660s	671.044us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	18.760s	921.458us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.020s	1.426ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.020s	1.426ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	58.290m	66.321ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.85	97.99	95.77	93.38	97.67	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.51906494682450466601533399987278550281282771960833030052846366414011706327685
      Line 6835, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26619445896 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26619445896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.29661954936597004937988900304264847681181463727309417437767745722415006825784
      Line 10193, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63769775790 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 63769775790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.82358647167330590080686374091002718563452567913647799198862044998911240135715
      Line 11721, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25658662855 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 25658662855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.lc_ctrl_stress_all_with_rand_reset.109802403976921000222204535548076959047087503321963191631262564169159600524825
      Line 37655, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 389029287377 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 389029287377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.64186799565291402939809480878005794846311043277610856771081311946502979913780
      Line 25944, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14848070404 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 14848070404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 44.lc_ctrl_stress_all.35547642611313252524056053640748596688909805929550332978260907622203321190749
      Line 7860, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 5903232077 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 5903232077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.8857590049708896398231562645420088463502996202061666385940652177933214178677
      Line 14127, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24681344139 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 24681344139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.06.25_11.32.22
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