LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.940s	176.277us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	189.114us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	16.765us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.720s	741.347us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.370s	22.861us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.700s	20.244us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	16.765us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	22.861us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.310s	328.632us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.090s	1.475ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	13.495us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.920s	135.884us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.080s	588.515us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_prog_failure	5.920s	135.884us	50	50	100.00
		lc_ctrl_errors	22.080s	588.515us	50	50	100.00
		lc_ctrl_security_escalation	16.280s	452.435us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.392m	4.457ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.300s	1.582ms	20	20	100.00
		lc_ctrl_jtag_errors	1.541m	3.762ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.980s	771.877us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	41.870s	3.707ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.300s	1.582ms	20	20	100.00
		lc_ctrl_jtag_errors	1.541m	3.762ms	20	20	100.00
		lc_ctrl_jtag_access	30.890s	11.014ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.210s	1.284ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.770s	215.927us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.770s	177.708us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	44.360s	3.857ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.140s	1.747ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.840s	282.077us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.900s	1.599ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.090s	70.728us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.200s	6.267ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	66.170us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.422m	26.828ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	25.428us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.590s	154.787us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.590s	154.787us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	189.114us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.765us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	22.861us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	105.621us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	189.114us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.765us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	22.861us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	105.621us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.400s	121.008us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.400s	121.008us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.090s	1.475ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.790s	1.546ms	50	50	100.00
		lc_ctrl_sec_cm	42.240s	1.058ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.280s	452.435us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.310s	328.632us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	41.870s	3.707ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.720s	1.822ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.720s	1.822ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.060s	701.722us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.940s	637.923us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.940s	637.923us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.341h	94.032ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.99	95.59	93.38	100.00	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.80441435832642395246930897876452209368631398788154917254718167070672287249174
      Line 11498, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35366386450 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 35366386450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.96760914311964093378734369752860793787622860084425770221927389081895563945306
      Line 29684, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22572070242 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22572070242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 5 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.103220348536697302692791761728739252691150381253112709901107196802992772867963
      Line 18485, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42722288217 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 42722288217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.lc_ctrl_stress_all_with_rand_reset.86765405389594730769559167189804756022808387110279327976168340342686840854228
      Line 41062, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39597701704 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 39597701704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.33598949169697580465161629262219420430052297341966899063925664040174256397258
      Line 24344, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 27.lc_ctrl_stress_all_with_rand_reset.82502101979392143406838331747808431333213933055422018775622388569853065527763
      Line 46168, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
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