LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.230s	177.268us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.300s	20.459us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	18.208us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.890s	257.218us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.650s	34.385us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.940s	44.369us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	18.208us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	34.385us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.890s	57.231us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.910s	781.909us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.070s	14.528us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.520s	103.040us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.800s	809.074us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_prog_failure	4.520s	103.040us	50	50	100.00
		lc_ctrl_errors	21.800s	809.074us	50	50	100.00
		lc_ctrl_security_escalation	14.830s	722.054us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.482m	17.320ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	34.800s	2.588ms	20	20	100.00
		lc_ctrl_jtag_errors	1.444m	6.093ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.030s	1.973ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.570s	1.263ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	34.800s	2.588ms	20	20	100.00
		lc_ctrl_jtag_errors	1.444m	6.093ms	20	20	100.00
		lc_ctrl_jtag_access	25.850s	1.123ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.120s	1.376ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.250s	1.031ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.550s	91.955us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.150s	5.943ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.920s	3.906ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	172.948us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.000s	103.151us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.780s	869.292us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	20.720s	1.711ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.410s	81.126us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.921m	33.451ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.040s	63.609us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.760s	159.692us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.760s	159.692us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.300s	20.459us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.208us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	34.385us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	118.391us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.300s	20.459us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.208us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	34.385us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	118.391us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
		lc_ctrl_tl_intg_err	3.520s	141.959us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.520s	141.959us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.910s	781.909us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.300s	719.181us	50	50	100.00
		lc_ctrl_sec_cm	39.840s	197.723us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.830s	722.054us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.890s	57.231us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.570s	1.263ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.380s	718.176us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.380s	718.176us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.780s	1.068ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.140s	533.216us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.140s	533.216us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.197h	120.652ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.99	95.95	93.38	100.00	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.114408427281988016453307017771232489623320907643414730470773422031107946521327
      Line 844, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 943036767 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 943036767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.57182572318088533994406379187934168120364340054105034628274598809567189258075
      Line 31998, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48721069737 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 48721069737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.70452827139703080354675441750241663483669431295678411771264590302993993858700
      Line 3478, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17130422960 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 17130422960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 18.lc_ctrl_stress_all.17386947955851203074649792145706640700777310326539791880786795520404488387352
      Line 3300, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 872525403 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 872525403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.06.29_09.38.35
• 2024.06.28_11.55.17
• 2024.06.27_11.12.39
• 2024.06.26_11.09.35
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