LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.720s	1.059ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	39.119us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	48.738us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.230s	372.017us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.700s	152.279us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.820s	123.562us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	48.738us	20	20	100.00
		lc_ctrl_csr_aliasing	1.700s	152.279us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.680s	78.642us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.770s	341.813us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	12.107us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.610s	110.025us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.760s	2.054ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_prog_failure	4.610s	110.025us	50	50	100.00
		lc_ctrl_errors	21.760s	2.054ms	50	50	100.00
		lc_ctrl_security_escalation	15.490s	412.393us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.248m	43.164ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.340s	1.797ms	20	20	100.00
		lc_ctrl_jtag_errors	1.752m	8.257ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.760s	2.441ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.690s	4.743ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.340s	1.797ms	20	20	100.00
		lc_ctrl_jtag_errors	1.752m	8.257ms	20	20	100.00
		lc_ctrl_jtag_access	26.030s	2.106ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.620s	1.205ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.740s	476.396us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.200s	123.573us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	24.330s	1.247ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.700s	3.217ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.000s	199.483us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.190s	253.654us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.110s	108.024us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	10.140s	4.348ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.090s	23.793us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	7.688m	82.257ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.470s	176.705us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.860s	664.852us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.860s	664.852us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	39.119us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	48.738us	20	20	100.00
		lc_ctrl_csr_aliasing	1.700s	152.279us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	48.855us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	39.119us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	48.738us	20	20	100.00
		lc_ctrl_csr_aliasing	1.700s	152.279us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	48.855us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
		lc_ctrl_tl_intg_err	4.540s	259.519us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.540s	259.519us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.770s	341.813us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.500s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.940s	432.962us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.490s	412.393us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.680s	78.642us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.690s	4.743ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.030s	3.021ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.030s	3.021ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.070s	1.867ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.340s	1.084ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.340s	1.084ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.462h	115.061ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.99	95.95	93.38	97.67	98.55	98.76	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.79118821181608256057359799831869929638824143525025284729898391738879300508156
      Line 14393, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69391978903 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 69391978903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.54088869699022389130646987672615487060415086215942946931190014646351220977535
      Line 5270, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4221429787 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4221429787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.22098604562491963150114619924910385953309841185461613643912269303148377940845
      Line 17453, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13187649093 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 13187649093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.lc_ctrl_stress_all_with_rand_reset.105802773386786418416031083023299676819240371186306148485912560715061629251641
      Line 14240, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72464963770 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 72464963770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 8.lc_ctrl_volatile_unlock_smoke.56774985841222124656916920114219081636440934601699405627325651763467270252398
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 120497025 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0xf6181604) == 0x1
        UVM_INFO @ 120497025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.18516321429907913553847440001591430887347258086424395627349606282020034321810
      Line 59126, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 74018727888 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 74018727888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.78488445332220327420293550915820102587844480022681234672967024845673569964139
      Line 39331, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.106460811203626217103718075651664749774359717185043162504432645598192360499910
      Line 41495, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45459298900 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 45459298900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.06.30_11.14.57
• 2024.06.29_09.38.35
• 2024.06.28_11.55.17
• 2024.06.27_11.12.39
• 2024.06.26_11.09.35
• 2024.06.25_11.32.22
• 2024.06.24_08.29.34