LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.530s	363.208us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.300s	153.935us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	61.340us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.670s	131.272us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.310s	75.959us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.440s	31.169us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	61.340us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	75.959us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.190s	79.760us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	14.520s	1.414ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	16.311us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.830s	2.257ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.280s	685.765us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_prog_failure	6.830s	2.257ms	50	50	100.00
		lc_ctrl_errors	24.280s	685.765us	50	50	100.00
		lc_ctrl_security_escalation	20.810s	2.642ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.276m	17.847ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	30.320s	2.275ms	20	20	100.00
		lc_ctrl_jtag_errors	1.165m	4.965ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.720s	1.802ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.260s	4.279ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	30.320s	2.275ms	20	20	100.00
		lc_ctrl_jtag_errors	1.165m	4.965ms	20	20	100.00
		lc_ctrl_jtag_access	20.090s	6.015ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.300s	1.786ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.130s	207.805us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.410s	182.030us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	39.620s	4.292ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.740s	802.672us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.510s	36.186us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.730s	117.860us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.990s	110.263us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.026m	10.003ms	8	10	80.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.590s	27.679us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.090m	53.457ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.300s	25.861us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.840s	587.578us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.840s	587.578us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.300s	153.935us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	61.340us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	75.959us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	80.924us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.300s	153.935us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	61.340us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	75.959us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	80.924us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
		lc_ctrl_tl_intg_err	4.320s	117.675us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.320s	117.675us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	14.520s	1.414ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.620s	3.857ms	50	50	100.00
		lc_ctrl_sec_cm	41.900s	211.588us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.810s	2.642ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.190s	79.760us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.260s	4.279ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.940s	746.984us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.940s	746.984us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.010s	825.316us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.440s	988.578us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.440s	988.578us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.014h	19.909ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.99	95.41	93.38	100.00	98.55	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.23002132174979699005227588872797280524766071639634525726828151666973111663987
      Line 11115, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27138443341 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27138443341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.7594710438577775550783751800055870046536534271992276267303322784928307402935
      Line 8903, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21477622455 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21477622455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 2 failures:

  • Test lc_ctrl_jtag_priority has 2 failures.

    • 0.lc_ctrl_jtag_priority.74443547548981842067066064665204730896765638675040981695732139210892997656745
      Line 837, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10002767816 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10002767816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.lc_ctrl_jtag_priority.47485770582345619011836855350079707423284208381812356433467756826956335101698
      Line 540, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10007881547 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10007881547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.91746491511123102783556484430910227429947851306052121800462766439295908371233
      Line 41957, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 157446541221 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 157446541221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.lc_ctrl_stress_all_with_rand_reset.111839156969431797833405771537079768279821321050248277763101621430896724165834
      Line 23719, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23911164015 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 23911164015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.18912801279882653291592634293159172355928595431309888787072225694073165233568
      Line 6562, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4468247989 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4468247989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 37.lc_ctrl_stress_all.40768575991918154239316175921278603255194452181475896999272396006430793346853
      Line 2506, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 15471228652 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 15471228652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.01_11.00.28
• 2024.06.30_11.14.57
• 2024.06.29_09.38.35
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