LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.490s	257.959us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	38.834us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	63.676us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.600s	260.284us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.620s	145.492us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.880s	43.470us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	63.676us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	145.492us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.340s	1.971ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.020s	425.597us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.050s	13.924us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.330s	93.086us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.000s	645.607us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_prog_failure	4.330s	93.086us	50	50	100.00
		lc_ctrl_errors	28.000s	645.607us	50	50	100.00
		lc_ctrl_security_escalation	16.420s	2.324ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.401m	41.739ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.690s	2.830ms	20	20	100.00
		lc_ctrl_jtag_errors	2.082m	18.853ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.250s	3.502ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.520s	1.308ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.690s	2.830ms	20	20	100.00
		lc_ctrl_jtag_errors	2.082m	18.853ms	20	20	100.00
		lc_ctrl_jtag_access	20.100s	13.993ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.840s	4.734ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.270s	218.955us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.560s	81.720us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	24.920s	1.107ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.730s	1.088ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.900s	38.287us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.300s	149.687us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.030s	250.035us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.290s	1.290ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.950s	98.249us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.779m	67.617ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.590s	39.586us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.730s	656.120us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.730s	656.120us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	38.834us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	63.676us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	145.492us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.560s	85.088us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	38.834us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	63.676us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	145.492us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.560s	85.088us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
		lc_ctrl_tl_intg_err	4.140s	111.933us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.140s	111.933us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.020s	425.597us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.850s	370.010us	50	50	100.00
		lc_ctrl_sec_cm	40.550s	503.127us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.420s	2.324ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.340s	1.971ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.520s	1.308ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.900s	2.353ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.900s	2.353ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	18.190s	2.865ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.560s	791.803us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.560s	791.803us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	31.288m	159.791ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.99	95.77	93.38	97.67	98.55	99.00	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 20 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.22195814824387480274244290388658187896575176922003787064770471475023089434017
    Line 30343, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 77315119210 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 77315119210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.107387414439725854582088155116192235888443312709249996823529311080243625531991
    Line 14489, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 207266753506 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 207266753506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.47173003049198432836588951132072399458319896853829891387907323226061748604025
    Line 47688, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48144919296 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 48144919296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.lc_ctrl_stress_all_with_rand_reset.63461685771802107227591822390057832568560058572670667441283962434753728339931
    Line 17285, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41900205684 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 41900205684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 17.lc_ctrl_stress_all_with_rand_reset.94251668546876975894233417125882428522002475195541982717653364626975771527008
    Line 30014, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65589208963 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 65589208963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.lc_ctrl_stress_all_with_rand_reset.47929560901367288448441748168331251929865326585471359114286366377591531411997
    Line 31801, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87134536481 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 87134536481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9ae10fb42`