LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.490s	947.253us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	22.729us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	17.836us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.770s	59.246us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.740s	267.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.450s	30.719us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	17.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.740s	267.565us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.730s	185.409us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.470s	3.540ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	14.398us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.430s	524.056us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.490s	1.087ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_prog_failure	5.430s	524.056us	50	50	100.00
		lc_ctrl_errors	22.490s	1.087ms	50	50	100.00
		lc_ctrl_security_escalation	17.230s	1.232ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.252m	55.983ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.990s	1.089ms	20	20	100.00
		lc_ctrl_jtag_errors	1.271m	11.462ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.640s	447.435us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.390s	3.666ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.990s	1.089ms	20	20	100.00
		lc_ctrl_jtag_errors	1.271m	11.462ms	20	20	100.00
		lc_ctrl_jtag_access	26.390s	1.204ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.740s	1.551ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.790s	801.136us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.130s	694.546us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.680s	4.907ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.640s	2.756ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.040s	200.704us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.670s	1.372ms	10	10	100.00
		lc_ctrl_jtag_alert_test	4.960s	3.875ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	35.300s	6.130ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	27.201us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	9.542m	16.962ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.410s	25.863us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.880s	171.417us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.880s	171.417us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	22.729us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	17.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.740s	267.565us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	69.079us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	22.729us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	17.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.740s	267.565us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	69.079us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
		lc_ctrl_tl_intg_err	6.060s	2.734ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.060s	2.734ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.470s	3.540ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.960s	370.865us	50	50	100.00
		lc_ctrl_sec_cm	38.920s	421.781us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.230s	1.232ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.730s	185.409us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.390s	3.666ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.100s	1.079ms	42	50	84.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.100s	1.079ms	42	50	84.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	31.980s	6.964ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.520s	752.920us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.520s	752.920us	50	50	100.00
V2S		TOTAL			167	175	95.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	45.409m	271.373ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.98	97.99	96.22	93.38	97.67	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.40018611675441640315088073509935921940613406752467015433490188004865952706519
      Line 30692, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40962781010 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 40962781010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.40317511473426422733489107131022476613458607690352347385379765801512217684268
      Line 28565, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46515790240 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 46515790240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 8 failures:

  • Test lc_ctrl_sec_mubi has 8 failures.

    • 15.lc_ctrl_sec_mubi.70502054343174222258208140040058376648178200010607787183055753841557976601437
      Line 1000, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 228561354 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 228561354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.lc_ctrl_sec_mubi.72968110672622817574070856830157236825440518663196775597791517692821793036485
      Line 1050, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 182535516 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 182535516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 40.lc_ctrl_stress_all_with_rand_reset.34901225906094273055171864078909266811148984272463006530694372563157782432145
      Line 2752, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7886672526 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7886672526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.lc_ctrl_stress_all_with_rand_reset.28880384989323316348217583772222456064667993954771210335268316217385444275780
      Line 5156, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2704923162 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2704923162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 10.lc_ctrl_stress_all_with_rand_reset.104125339966769073987794094752074611564763288006234704987213632457032537065872
      Line 19587, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8770423493 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 8770423493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.96340986851615632766319740933781254792147139912769143881647653637419105483825
      Line 13391, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21203006450 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 21203006450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.109811868257814479266841055526291017431905709540035751188214334168030805883426
      Line 17850, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14726118220 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 14726118220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 42.lc_ctrl_volatile_unlock_smoke.508129969838036295938784046158213061198425940345435789731916039695119816508
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 133628787 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0xddf6d04) == 0x1
        UVM_INFO @ 133628787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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