LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.960s	105.234us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.310s	18.885us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	19.146us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.680s	64.260us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.530s	27.876us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.110s	34.683us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	19.146us	20	20	100.00
		lc_ctrl_csr_aliasing	1.530s	27.876us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.220s	648.315us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.510s	1.115ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	13.797us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.440s	104.213us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	17.610s	1.439ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_prog_failure	4.440s	104.213us	50	50	100.00
		lc_ctrl_errors	17.610s	1.439ms	50	50	100.00
		lc_ctrl_security_escalation	17.310s	2.010ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.399m	9.192ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.840s	690.773us	20	20	100.00
		lc_ctrl_jtag_errors	1.917m	4.577ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.090s	466.968us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.670s	3.627ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.840s	690.773us	20	20	100.00
		lc_ctrl_jtag_errors	1.917m	4.577ms	20	20	100.00
		lc_ctrl_jtag_access	33.080s	1.496ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.120s	1.037ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.550s	248.154us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.290s	160.297us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.330s	6.433ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.800s	2.408ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	92.749us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.890s	604.002us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.570s	483.219us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	17.270s	3.270ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.180s	16.062us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.398m	90.806ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	50.240us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.520s	623.966us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.520s	623.966us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.310s	18.885us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	19.146us	20	20	100.00
		lc_ctrl_csr_aliasing	1.530s	27.876us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	161.731us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.310s	18.885us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	19.146us	20	20	100.00
		lc_ctrl_csr_aliasing	1.530s	27.876us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	161.731us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
		lc_ctrl_tl_intg_err	4.200s	119.262us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.200s	119.262us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.510s	1.115ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.300s	1.847ms	50	50	100.00
		lc_ctrl_sec_cm	25.210s	244.585us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.310s	2.010ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.220s	648.315us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.670s	3.627ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.620s	4.685ms	42	50	84.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.620s	4.685ms	42	50	84.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.780s	971.219us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.910s	738.933us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.910s	738.933us	50	50	100.00
V2S		TOTAL			167	175	95.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	43.645m	99.033ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.99	95.86	93.38	97.67	98.55	98.76	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.1897624771703146361528255339464509978383764360398877874944651059330643406641
      Line 48981, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 352466157274 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 352466157274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.64820499590464640310492246438681354105438513624939000996833730479998714170133
      Line 7003, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66579386587 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 66579386587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 8 failures:
  • Test lc_ctrl_sec_mubi has 8 failures.

    • 4.lc_ctrl_sec_mubi.6331508799958259845133339382730628102898371405353941397043761771189697297523
      Line 2576, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 499561834 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 499561834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_sec_mubi.11000234435631841304998300080614313400414056978018855934397356693331729197451
      Line 1856, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  98693065 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  98693065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.15998611503805771701792465089432326541655843809630376340344839604657265074510
      Line 13182, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63494325100 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 63494325100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.lc_ctrl_stress_all_with_rand_reset.41084078259702262955061950982508370813861249202722729346207233770911064403043
      Line 20228, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7161338146 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7161338146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

Past Results

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