LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.830s	201.755us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.060s	42.954us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	60.974us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.190s	96.629us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.350s	18.421us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.860s	105.514us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	60.974us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	18.421us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.270s	401.346us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.600s	373.151us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	11.070us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.790s	220.895us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.390s	549.175us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_prog_failure	4.790s	220.895us	50	50	100.00
		lc_ctrl_errors	22.390s	549.175us	50	50	100.00
		lc_ctrl_security_escalation	16.710s	915.515us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.910m	15.286ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.330s	3.735ms	20	20	100.00
		lc_ctrl_jtag_errors	2.162m	4.902ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.020s	1.628ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.600s	1.626ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.330s	3.735ms	20	20	100.00
		lc_ctrl_jtag_errors	2.162m	4.902ms	20	20	100.00
		lc_ctrl_jtag_access	17.220s	5.990ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.790s	2.518ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.240s	456.663us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.190s	1.576ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.910s	5.104ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.650s	4.438ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.140s	53.923us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.540s	587.419us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.390s	80.351us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	17.410s	679.998us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.370s	18.576us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.436m	24.679ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.590s	53.112us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.810s	509.028us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.810s	509.028us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.060s	42.954us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	60.974us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	18.421us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.560s	103.337us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.060s	42.954us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	60.974us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	18.421us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.560s	103.337us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
		lc_ctrl_tl_intg_err	4.910s	165.294us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.910s	165.294us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.600s	373.151us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.660s	279.409us	50	50	100.00
		lc_ctrl_sec_cm	44.410s	232.192us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.710s	915.515us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.270s	401.346us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.600s	1.626ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.560s	1.097ms	40	50	80.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.560s	1.097ms	40	50	80.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	30.360s	7.882ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.150s	7.669ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.150s	7.669ms	50	50	100.00
V2S		TOTAL			165	175	94.29
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	37.769m	28.291ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.36	97.99	96.13	93.38	100.00	98.55	99.00	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.69214467149282194931774010904970041113172899033682333641221731343864536169604
      Line 5683, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4054921569 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4054921569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.32524320586457858979045120841361277187468798724839924464670806807057879627
      Line 23796, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72748895599 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 72748895599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 10 failures:
  • Test lc_ctrl_sec_mubi has 10 failures.

    • 1.lc_ctrl_sec_mubi.91632318765098285880915669066005844917006107005251458170178429875937575337854
      Line 1674, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 236621519 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 236621519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_sec_mubi.78394991835917646257472960924239045299344220330444534654516262339559754594481
      Line 1440, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 114002078 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 114002078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 8.lc_ctrl_stress_all.95102423809478304759623545940969142924971722209800789181680553705942436385197
      Line 8518, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3591021502 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3591021502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all.773310289410307585312095084805173335742862167891536521680963869468446354341
      Line 1460, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1340503274 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1340503274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.60358326848898310519187620172990398468825278856918058511728155879964097608251
      Line 24510, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26236391275 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 26236391275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.04_11.17.33
• 2024.07.03_01.51.11
• 2024.07.02_10.46.37
• 2024.07.02_04.16.05
• 2024.07.01_11.00.28
• 2024.06.30_11.14.57
• 2024.06.29_09.38.35