LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.840s	350.914us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	16.464us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	15.954us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.420s	271.608us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.260s	278.502us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.330s	63.347us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	15.954us	20	20	100.00
		lc_ctrl_csr_aliasing	1.260s	278.502us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.140s	345.269us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.200s	1.433ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	61.508us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.450s	231.441us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.280s	3.608ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_prog_failure	6.450s	231.441us	50	50	100.00
		lc_ctrl_errors	25.280s	3.608ms	50	50	100.00
		lc_ctrl_security_escalation	16.970s	3.959ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.402m	7.309ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.620s	520.663us	20	20	100.00
		lc_ctrl_jtag_errors	2.165m	19.585ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.680s	720.652us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.520s	2.220ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.620s	520.663us	20	20	100.00
		lc_ctrl_jtag_errors	2.165m	19.585ms	20	20	100.00
		lc_ctrl_jtag_access	32.050s	1.400ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.470s	1.076ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.220s	422.440us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.670s	199.905us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	40.700s	1.926ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.360s	1.455ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.000s	187.918us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.090s	966.934us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.130s	65.942us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	23.070s	1.004ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.750s	57.304us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.995m	144.451ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.490s	34.717us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.500s	145.871us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.500s	145.871us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	16.464us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	15.954us	20	20	100.00
		lc_ctrl_csr_aliasing	1.260s	278.502us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.880s	187.632us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	16.464us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	15.954us	20	20	100.00
		lc_ctrl_csr_aliasing	1.260s	278.502us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.880s	187.632us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
		lc_ctrl_tl_intg_err	4.990s	223.921us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.990s	223.921us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.200s	1.433ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.390s	864.684us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	198.982us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.970s	3.959ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.140s	345.269us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.520s	2.220ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.520s	1.283ms	40	50	80.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.520s	1.283ms	40	50	80.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.810s	869.980us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.570s	1.146ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.570s	1.146ms	50	50	100.00
V2S		TOTAL			165	175	94.29
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.836h	21.633ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			985	1030	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.99	95.41	93.38	100.00	98.55	98.76	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.109464440987528622480995688846624076033342408870759600585128747392690658506410
    Line 20777, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28111109559 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28111109559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.lc_ctrl_stress_all_with_rand_reset.54517316919726960093233740757330654871428385422933771338476915851051828275524
    Line 23774, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 206886854059 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 206886854059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 10 failures:
- Test lc_ctrl_sec_mubi has 10 failures.
  - 1.lc_ctrl_sec_mubi.32680738543500499467122717520868032295984550167667755152528749259102281690047
    Line 460, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @  14006278 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  14006278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_sec_mubi.22758500094112722789297988149433893975269165355534729337120441065102674677603
    Line 3338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 244201543 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 244201543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 11.lc_ctrl_stress_all_with_rand_reset.63741510510918034315942223649287191325125543256956029786441044688960750029375
    Line 40953, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 16.lc_ctrl_stress_all_with_rand_reset.57030163765716350278257528057493344405710273747387228111784469048368598984238
    Line 42291, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - ... and 2 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.112666490580696628749329362706049794825955553090358154171361828628185870229320
    Line 21735, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42541347916 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 42541347916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.lc_ctrl_stress_all_with_rand_reset.71825467929845670082891157649641642318719060230384281582017970590253035890021
    Line 7246, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52205678115 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 52205678115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_stress_all has 1 failures.
  - 31.lc_ctrl_stress_all.110430243571311713995757902551802115314070599084189858712775429057953059103778
    Line 2805, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 969075176 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 969075176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 24.lc_ctrl_stress_all_with_rand_reset.40173612816148615696651934034264813989665340532695274465090035840338429215619
    Line 30840, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22454773919 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 22454773919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.lc_ctrl_stress_all_with_rand_reset.9594274502890724308562248540945234207374564157885636214418707385853441619090
    Line 36868, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 96691916685 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 96691916685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.lc_ctrl_stress_all_with_rand_reset.87478859010392025717909073378842757269759716580580185110527355722934329898904
    Line 8355, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19173413104 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 19173413104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 23.lc_ctrl_stress_all_with_rand_reset.100778192693050638447380771682492021734803310238285387184498676032955343951661
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c0ca5403-f84e-43e9-b8b5-3b1c04671a69
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9edf84e236`