LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.020s	205.854us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.390s	20.720us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	18.030us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.250s	189.347us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.370s	35.280us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.350s	30.248us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	18.030us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	35.280us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.830s	80.010us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.320s	1.313ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	15.201us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.820s	320.222us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.670s	776.903us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_prog_failure	4.820s	320.222us	50	50	100.00
		lc_ctrl_errors	28.670s	776.903us	50	50	100.00
		lc_ctrl_security_escalation	18.240s	3.386ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.007m	73.324ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.840s	1.920ms	20	20	100.00
		lc_ctrl_jtag_errors	1.199m	2.628ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.740s	2.001ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.060s	1.759ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.840s	1.920ms	20	20	100.00
		lc_ctrl_jtag_errors	1.199m	2.628ms	19	20	95.00
		lc_ctrl_jtag_access	29.860s	5.324ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.520s	1.492ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.610s	161.663us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.730s	2.199ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.390s	1.247ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	32.240s	2.948ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.480s	193.205us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.470s	528.717us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.120s	53.561us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	59.370s	10.561ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.420s	22.470us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.815m	70.908ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.540s	89.637us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.640s	205.375us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.640s	205.375us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.390s	20.720us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	18.030us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	35.280us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	93.906us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.390s	20.720us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	18.030us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	35.280us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	93.906us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
		lc_ctrl_tl_intg_err	4.260s	103.849us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.260s	103.849us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.320s	1.313ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.740s	1.062ms	50	50	100.00
		lc_ctrl_sec_cm	39.910s	221.008us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.240s	3.386ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.830s	80.010us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.060s	1.759ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.190s	2.010ms	43	50	86.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.190s	2.010ms	43	50	86.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.140s	1.416ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.080s	614.675us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.080s	614.675us	50	50	100.00
V2S		TOTAL			168	175	96.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.891h	528.164ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			991	1030	96.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.99	95.68	93.38	100.00	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.41042410629029098044525898111982018835553280835227084508589620187133701375794
      Line 14604, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75177203628 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 75177203628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.114754780129391856578118652374040482712852893202041257857106384640213626111468
      Line 3689, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4086765380 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4086765380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 7 failures:

  • Test lc_ctrl_sec_mubi has 7 failures.

    • 19.lc_ctrl_sec_mubi.69365823095318903224941903580699879445061985601566061506613216654698231012491
      Line 766, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  79566312 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  79566312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_sec_mubi.86023410144189890571063337589475223495239623986766349853551270040050828496061
      Line 3996, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 326199018 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 326199018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 2.lc_ctrl_jtag_errors.78925218661618388330996196594738759610742454195570340163453023912734469335778
      Line 365, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 858267695 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 858267695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.62762711350341625254700111008036256072100015890279912815786009078774520451646
      Line 6522, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7268199371 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 7268199371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.24266738963593093379697753440035724712900836319278560342288111402002069785902
      Line 36697, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 10.lc_ctrl_stress_all_with_rand_reset.68721138531925936867700480457388851990542232142187805142690053056739522607989
      Line 48210, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.5677758721353741207387415616998578358332252707534782278952900615805740673562
      Line 28210, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 59366772028 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 59366772028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_stress_all_with_rand_reset.53912338433108138697686710093344072331785290687584170991683170964328556844824
      Line 1751, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11657485596 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11657485596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.06_10.43.55
• 2024.07.05_11.08.23
• 2024.07.04_11.17.33
• 2024.07.03_01.51.11
• 2024.07.02_10.46.37
• 2024.07.02_04.16.05
• 2024.07.01_11.00.28