LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.420s	199.783us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	22.230us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	13.927us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.620s	93.977us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.760s	709.681us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.970s	97.193us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	13.927us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	709.681us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.420s	1.070ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.290s	1.674ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	11.903us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.180s	620.130us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.760s	1.618ms	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_prog_failure	6.180s	620.130us	50	50	100.00
		lc_ctrl_errors	28.760s	1.618ms	48	50	96.00
		lc_ctrl_security_escalation	16.060s	451.158us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.194m	7.578ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.860s	3.896ms	20	20	100.00
		lc_ctrl_jtag_errors	1.397m	3.351ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.820s	705.133us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.390s	1.199ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.860s	3.896ms	20	20	100.00
		lc_ctrl_jtag_errors	1.397m	3.351ms	20	20	100.00
		lc_ctrl_jtag_access	28.430s	4.895ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.380s	4.518ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.170s	207.721us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.440s	344.798us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	39.550s	3.475ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.460s	1.826ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.880s	40.432us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.200s	190.443us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.700s	78.045us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	59.280s	10.756ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.230s	15.983us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.829m	86.256ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.280s	81.535us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.380s	474.088us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.380s	474.088us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	22.230us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	13.927us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	709.681us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	45.591us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	22.230us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	13.927us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	709.681us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	45.591us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
		lc_ctrl_tl_intg_err	6.330s	224.060us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.330s	224.060us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.290s	1.674ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.940s	372.981us	50	50	100.00
		lc_ctrl_sec_cm	37.390s	1.111ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.060s	451.158us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.420s	1.070ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.390s	1.199ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.700s	791.667us	41	50	82.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.700s	791.667us	41	50	82.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.580s	2.434ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.040s	2.781ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.040s	2.781ms	50	50	100.00
V2S		TOTAL			166	175	94.86
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	25.444m	170.098ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			990	1030	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	97.99	95.77	93.38	100.00	98.55	98.76	96.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.86047072619542977567075194035341426861570158877345444734543171850848947485706
      Line 14541, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12735965662 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12735965662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.79693358362380773321558583580778256949589138778879820470238596295115063349805
      Line 22827, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16714043777 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16714043777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 9 failures:

  • Test lc_ctrl_sec_mubi has 9 failures.

    • 8.lc_ctrl_sec_mubi.87547172629142350711498376135689013013633268612157407651546247556851572165958
      Line 2674, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 221922077 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 221922077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.lc_ctrl_sec_mubi.107166407024841996188230535187600287944921858507774504870332379887815225153902
      Line 4818, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 440845563 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 440845563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.79532238545435269062179350593177464492293005695913376186921131032379413967939
      Line 8611, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3454405305 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 3454405305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.lc_ctrl_stress_all_with_rand_reset.9486670267573829268803046085101083999830593311037539964553453835179596882394
      Line 19842, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 95802882653 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 95802882653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_errors has 2 failures.

    • 24.lc_ctrl_errors.96862578694788976368609856976364837369882414364810207345035278287326114397870
      Line 1077, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 240971777 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 240971777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 31.lc_ctrl_errors.5066426813236110093861185698917338985612058330308635516140873942969959704759
      Line 1308, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 261501925 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 261501925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.60430725175205253561604056272560163783053764615422787813029030667043836004297
      Line 5007, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75988186817 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 75988186817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.2078856349676993616731453466347489943613131661101779477783556775110815357433
      Line 42720, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.07_10.36.05
• 2024.07.06_10.43.55
• 2024.07.05_11.08.23
• 2024.07.04_11.17.33
• 2024.07.03_01.51.11
• 2024.07.02_10.46.37
• 2024.07.02_04.16.05