LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.930s	2.152ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	95.493us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	20.252us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.070s	368.511us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.660s	124.165us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.260s	138.323us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	20.252us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	124.165us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.230s	162.206us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.690s	352.713us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	34.571us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.460s	998.516us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.890s	2.087ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_prog_failure	6.460s	998.516us	50	50	100.00
		lc_ctrl_errors	21.890s	2.087ms	50	50	100.00
		lc_ctrl_security_escalation	15.820s	537.474us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.389m	4.771ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.440s	935.179us	20	20	100.00
		lc_ctrl_jtag_errors	1.410m	3.058ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.980s	641.707us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.080s	4.392ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.440s	935.179us	20	20	100.00
		lc_ctrl_jtag_errors	1.410m	3.058ms	20	20	100.00
		lc_ctrl_jtag_access	31.590s	11.257ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.080s	1.067ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.370s	329.577us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.460s	310.070us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.530s	3.715ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.050s	3.457ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.190s	48.597us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.900s	286.141us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.590s	105.543us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.480s	1.836ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.590s	43.309us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.581m	38.526ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	91.359us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.910s	1.338ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.910s	1.338ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	95.493us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	20.252us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	124.165us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	105.793us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	95.493us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	20.252us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	124.165us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	105.793us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
		lc_ctrl_tl_intg_err	4.530s	121.810us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.530s	121.810us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.690s	352.713us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.620s	295.185us	50	50	100.00
		lc_ctrl_sec_cm	41.170s	363.974us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.820s	537.474us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.230s	162.206us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.080s	4.392ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.540s	748.851us	38	50	76.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.540s	748.851us	38	50	76.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	30.800s	1.255ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.080s	2.311ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.080s	2.311ms	50	50	100.00
V2S		TOTAL			163	175	93.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.990h	34.050ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			993	1030	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.99	95.59	93.38	97.67	98.55	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.96260178776126136492661024327454012501191864292792003058088581623251187464252
      Line 1273, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1703982633 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1703982633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.17315470720996478716644453712361866559697835519151089663147716562413963675731
      Line 10897, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34003961135 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 34003961135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 12 failures:

  • Test lc_ctrl_sec_mubi has 12 failures.

    • 5.lc_ctrl_sec_mubi.76264405203813774730810633582767474593036797807239566840827054702385350617194
      Line 544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 116103702 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 116103702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.lc_ctrl_sec_mubi.91218143646519182814739740454481059062965176052566325723837562711847618998285
      Line 1692, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 112436569 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 112436569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.38542751682374075059397585704069328135939632329757567074988045622707068473535
      Line 40916, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 24.lc_ctrl_stress_all_with_rand_reset.45119251710166822451010212554648990356409509190948306559124092141502211772142
      Line 60504, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.23425820375565838372095850890949446063704251221754092141681312602405787986279
      Line 29134, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 192241437166 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 192241437166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 40.lc_ctrl_stress_all_with_rand_reset.107321329314519014560161120783181597559617109793102224563280859594069093807194
      Line 53886, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 90943418939 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 90943418939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.08_10.13.48
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