LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.230s	1.526ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.290s	21.085us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	14.778us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.480s	240.495us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.750s	31.414us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.990s	170.496us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	14.778us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	31.414us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.930s	1.210ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.780s	809.404us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	12.188us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	8.050s	879.096us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	17.640s	410.247us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_prog_failure	8.050s	879.096us	50	50	100.00
		lc_ctrl_errors	17.640s	410.247us	50	50	100.00
		lc_ctrl_security_escalation	16.710s	860.550us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.785m	3.235ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.770s	3.252ms	20	20	100.00
		lc_ctrl_jtag_errors	1.262m	5.817ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.990s	4.088ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.180s	1.098ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.770s	3.252ms	20	20	100.00
		lc_ctrl_jtag_errors	1.262m	5.817ms	20	20	100.00
		lc_ctrl_jtag_access	35.060s	9.561ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	24.590s	6.792ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.210s	1.015ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.490s	2.848ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.550s	2.599ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.330s	2.107ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.000s	45.722us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.870s	1.122ms	10	10	100.00
		lc_ctrl_jtag_alert_test	1.970s	99.433us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	54.550s	9.814ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	77.562us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.342m	15.966ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	65.916us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.690s	86.746us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.690s	86.746us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.290s	21.085us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	14.778us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	31.414us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	154.239us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.290s	21.085us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	14.778us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	31.414us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	154.239us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
		lc_ctrl_tl_intg_err	5.190s	759.966us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.190s	759.966us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.780s	809.404us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.090s	338.796us	50	50	100.00
		lc_ctrl_sec_cm	40.590s	907.969us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.710s	860.550us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.930s	1.210ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.180s	1.098ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.950s	526.366us	38	50	76.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.950s	526.366us	38	50	76.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.080s	1.705ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.790s	1.934ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.790s	1.934ms	50	50	100.00
V2S		TOTAL			163	175	93.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	53.278m	53.577ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			990	1030	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	97.99	96.04	93.38	100.00	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.63525973366289484897352448103085130915962517761119695333307158374005115216893
      Line 12475, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7297279896 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7297279896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.51219003912482579523530868412610540366996021925812776582691140855903121196916
      Line 8589, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5493385441 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5493385441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 12 failures:
  • Test lc_ctrl_sec_mubi has 12 failures.

    • 0.lc_ctrl_sec_mubi.93582297664529506936503899299593972438595733234004727427183309387550451627648
      Line 2718, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 410065850 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 410065850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_sec_mubi.18311324348636004999500379877550601231716243904596838726444147366262161520075
      Line 3576, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 3336023413 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3336023413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.68731810359494680457436429072865900867449837564226392846592544929178049075968
      Line 46501, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.10_10.43.37
• 2024.07.08_10.13.48
• 2024.07.07_10.36.05
• 2024.07.06_10.43.55
• 2024.07.05_11.08.23
• 2024.07.04_11.17.33
• 2024.07.03_01.51.11