LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.180s	1.503ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.300s	21.003us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	18.613us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.650s	1.065ms	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.750s	138.055us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.330s	32.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	18.613us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	138.055us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.880s	62.726us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.640s	1.426ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	39.780us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.760s	591.554us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.030s	4.127ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_prog_failure	4.760s	591.554us	50	50	100.00
		lc_ctrl_errors	22.030s	4.127ms	49	50	98.00
		lc_ctrl_security_escalation	15.840s	845.277us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.466m	4.979ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.320s	3.137ms	20	20	100.00
		lc_ctrl_jtag_errors	1.958m	7.937ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.100s	475.000us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.400s	2.509ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.320s	3.137ms	20	20	100.00
		lc_ctrl_jtag_errors	1.958m	7.937ms	20	20	100.00
		lc_ctrl_jtag_access	23.760s	4.096ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.560s	13.602ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.470s	2.459ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.630s	84.079us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	41.750s	12.326ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.560s	2.656ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	42.287us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.640s	2.130ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.190s	63.712us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	23.290s	1.062ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.390s	20.273us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.726m	28.554ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.060s	136.283us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.240s	117.803us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.240s	117.803us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.300s	21.003us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.613us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	138.055us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.260s	105.332us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.300s	21.003us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.613us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	138.055us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.260s	105.332us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
		lc_ctrl_tl_intg_err	4.130s	105.207us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.130s	105.207us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.640s	1.426ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.110s	395.739us	50	50	100.00
		lc_ctrl_sec_cm	40.370s	236.350us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.840s	845.277us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.880s	62.726us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.400s	2.509ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.250s	489.506us	39	50	78.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.250s	489.506us	39	50	78.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.780s	951.229us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.250s	988.540us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.250s	988.540us	50	50	100.00
V2S		TOTAL			164	175	93.71
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	37.965m	104.945ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			991	1030	96.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	97.99	95.95	93.38	100.00	98.55	99.00	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 19 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.40163778906447351945989043390702255306099717810876274140169783215965784100366
    Line 30419, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79556565372 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 79556565372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.lc_ctrl_stress_all_with_rand_reset.1632784929042272743981136852438664613493483057219201790715725418629499889707
    Line 19715, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42717031324 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42717031324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 11 failures:
- Test lc_ctrl_sec_mubi has 11 failures.
  - 5.lc_ctrl_sec_mubi.87134241181036738837254593963368923136435826251261899863214170296839433883520
    Line 634, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 129866530 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 129866530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.lc_ctrl_sec_mubi.79807496417418408450131049004347433650263544696967744909004039976941988214996
    Line 2356, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 562338284 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 562338284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 16.lc_ctrl_stress_all_with_rand_reset.110125661010012033298973692945631277351127798081285184581940747541403489478586
    Line 13616, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10153231242 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 10153231242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.lc_ctrl_stress_all_with_rand_reset.71800300226081411166875434528939248522441997235512844563325372143989221416402
    Line 35801, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111544694084 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 111544694084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 31.lc_ctrl_stress_all_with_rand_reset.1304252781036512677251666717206230122892495418923822399496497241928003781858
    Line 29195, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24695941261 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 24695941261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.lc_ctrl_stress_all_with_rand_reset.102855275387296120788396279835887896900343229049883182893610438832191010552713
    Line 6665, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3565774097 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3565774097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_errors has 1 failures.
  - 39.lc_ctrl_errors.78395688567160526331989355221192404989882139411260421935052001366333610140936
    Line 999, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @  63915846 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  63915846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 19.lc_ctrl_stress_all_with_rand_reset.110312604702932679115658154472987669846667398513962698737533266112844587736176
    Line 57863, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 76835551678 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 76835551678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.lc_ctrl_stress_all_with_rand_reset.35715024623848374271050835657541175398828644736470625294951266082056087358335
    Line 44471, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111771486304 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 111771486304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:
- Test lc_ctrl_jtag_priority has 1 failures.
  - 2.lc_ctrl_jtag_priority.71152104262460123131695089611113323586606166988949501171437388434708446385345
    Line 461, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_priority/latest/run.log
```
  UVM_FATAL @ 10013038460 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
  UVM_INFO @ 10013038460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `edf2fd5092`