LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.830s	574.678us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.280s	20.965us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.060s	26.726us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.090s	210.798us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.290s	285.875us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.280s	30.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.060s	26.726us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	285.875us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.390s	56.883us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.830s	398.099us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	11.237us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.670s	348.834us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.990s	754.749us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_prog_failure	4.670s	348.834us	50	50	100.00
		lc_ctrl_errors	27.990s	754.749us	50	50	100.00
		lc_ctrl_security_escalation	16.620s	492.771us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.930m	7.215ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.200s	794.733us	20	20	100.00
		lc_ctrl_jtag_errors	2.172m	4.933ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.710s	1.456ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.480s	1.920ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.200s	794.733us	20	20	100.00
		lc_ctrl_jtag_errors	2.172m	4.933ms	20	20	100.00
		lc_ctrl_jtag_access	26.140s	1.109ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	23.250s	783.936us	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.520s	174.443us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.490s	357.894us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.280s	4.393ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.810s	1.177ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.750s	429.880us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.750s	180.360us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.160s	1.232ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.160s	1.061ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.560s	103.225us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	6.263m	10.734ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.280s	205.193us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.220s	136.803us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.220s	136.803us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.280s	20.965us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	26.726us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	285.875us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.640s	188.313us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.280s	20.965us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	26.726us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	285.875us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.640s	188.313us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
		lc_ctrl_tl_intg_err	5.150s	152.752us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.150s	152.752us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.830s	398.099us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.520s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	40.310s	827.518us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.620s	492.771us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.390s	56.883us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.480s	1.920ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.290s	1.289ms	40	50	80.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.290s	1.289ms	40	50	80.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.610s	1.103ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.660s	4.711ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.660s	4.711ms	50	50	100.00
V2S		TOTAL			165	175	94.29
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	30.655m	19.585ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.99	95.59	93.38	97.67	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.18853324207264055532182291210307124666264599138016848639350558529979033401627
      Line 15388, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70203146004 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 70203146004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.43774497184452270580767410520828621421445436180168496530132844507263589124013
      Line 955, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1191679749 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1191679749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 10 failures:

  • Test lc_ctrl_sec_mubi has 10 failures.

    • 0.lc_ctrl_sec_mubi.86132612909604769406588830377345376430599261996388307008187179096535868600036
      Line 1948, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 288596709 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 288596709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.lc_ctrl_sec_mubi.33236332724299301698858358041650507586715523851695993108606650352183664423840
      Line 2624, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 342273445 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 342273445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.22636166567832045711267120807167648995208077680424007577397216656851126224076
      Line 21554, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20948140092 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 20948140092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.lc_ctrl_stress_all_with_rand_reset.85725201924268833149120440488072012677372589920494368664759594275227621908113
      Line 25782, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 80307897445 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 80307897445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.40747553674530699856930944207257210196273430143669348563053717443678644044399
      Line 33009, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 44.lc_ctrl_volatile_unlock_smoke.101630949946763224166513639383511245464557325164347809887672414958067609289543
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 151612293 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x1ffc3604) == 0x1
        UVM_INFO @ 151612293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.90518187777001088592307205188325707051879742133791597615143750835149226645110
      Line 17596, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7867835126 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 7867835126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.07.08_10.13.48
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