LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.620s	795.154us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.280s	33.319us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	33.580us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.100s	379.159us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.330s	200.211us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.780s	40.468us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	33.580us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	200.211us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.450s	177.303us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	29.080s	499.797us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	11.978us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.450s	116.749us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.820s	3.323ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_prog_failure	5.450s	116.749us	50	50	100.00
		lc_ctrl_errors	22.820s	3.323ms	50	50	100.00
		lc_ctrl_security_escalation	15.750s	436.648us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.568m	9.776ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.290s	2.449ms	20	20	100.00
		lc_ctrl_jtag_errors	1.927m	4.332ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.800s	722.988us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.450s	880.777us	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.290s	2.449ms	20	20	100.00
		lc_ctrl_jtag_errors	1.927m	4.332ms	20	20	100.00
		lc_ctrl_jtag_access	25.670s	1.122ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.040s	10.281ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.260s	96.042us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.730s	93.106us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.480s	1.520ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.650s	4.017ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.680s	149.593us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.050s	465.301us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.130s	122.362us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	10.060s	1.757ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.190s	27.299us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.122m	20.239ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.370s	22.490us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.540s	458.199us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.540s	458.199us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.280s	33.319us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	33.580us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	200.211us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	47.868us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.280s	33.319us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	33.580us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	200.211us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	47.868us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
		lc_ctrl_tl_intg_err	4.380s	477.056us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.380s	477.056us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	29.080s	499.797us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.400s	1.537ms	50	50	100.00
		lc_ctrl_sec_cm	37.820s	234.157us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.750s	436.648us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.450s	177.303us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.450s	880.777us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.450s	1.321ms	42	50	84.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.450s	1.321ms	42	50	84.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.280s	3.946ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.710s	500.888us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.710s	500.888us	50	50	100.00
V2S		TOTAL			167	175	95.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.444h	49.093ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			996	1030	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.99	96.04	93.38	100.00	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.39941576269912497781515842676771761636418567434195881221467036599315414917408
      Line 27845, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 95004489938 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 95004489938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.54391546742611978494389599968628241648125678160634006056732908149676930221770
      Line 5455, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24125783043 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24125783043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 8 failures:

  • Test lc_ctrl_sec_mubi has 8 failures.

    • 1.lc_ctrl_sec_mubi.41519346845722607752394816351436234152616346202223297613600844664682313120664
      Line 368, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @   3125642 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @   3125642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_sec_mubi.102950184506024458879270782732070463744621880512336498991961723866512347500182
      Line 2542, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 380566824 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 380566824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.64053593942455582883387884675632228144188531327273910884776295281273205682140
      Line 27477, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10425448242 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 10425448242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.lc_ctrl_stress_all_with_rand_reset.27243201552019476530449965293512808187597706608071219370000622966858277623920
      Line 20157, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 54833552589 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 54833552589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 5.lc_ctrl_stress_all.81658363131792674966490506752527405332932684527760799888540238064430548518969
      Line 8981, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 4852605382 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4852605382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.7661618781031000332107531366322070792759414854909682092797491548256963260761
      Line 64456, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 103493151058 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 103493151058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.37575044533780668515254804788558119170920832722119947283725909351195613064491
      Line 44874, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.13_08.23.58
• 2024.07.12_09.10.35
• 2024.07.11_10.36.05
• 2024.07.10_10.43.37
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