LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.550s	255.779us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.050s	69.353us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	20.146us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.060s	187.986us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.970s	44.255us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.950s	39.545us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	20.146us	20	20	100.00
		lc_ctrl_csr_aliasing	1.970s	44.255us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.540s	1.067ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.500s	1.379ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	12.555us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.720s	929.940us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.300s	453.735us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_prog_failure	4.720s	929.940us	50	50	100.00
		lc_ctrl_errors	19.300s	453.735us	50	50	100.00
		lc_ctrl_security_escalation	15.500s	435.934us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.097m	11.405ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.660s	3.525ms	20	20	100.00
		lc_ctrl_jtag_errors	1.747m	3.824ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.680s	834.642us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.940s	4.139ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.660s	3.525ms	20	20	100.00
		lc_ctrl_jtag_errors	1.747m	3.824ms	20	20	100.00
		lc_ctrl_jtag_access	22.060s	14.986ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.470s	2.101ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.850s	330.422us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.420s	723.982us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	20.130s	2.494ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.750s	1.228ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.570s	54.536us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.540s	212.337us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.230s	69.495us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	8.020s	2.656ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.360s	40.829us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.036m	15.808ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.430s	108.222us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.180s	159.647us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.180s	159.647us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.050s	69.353us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	20.146us	20	20	100.00
		lc_ctrl_csr_aliasing	1.970s	44.255us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.180s	51.891us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.050s	69.353us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	20.146us	20	20	100.00
		lc_ctrl_csr_aliasing	1.970s	44.255us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.180s	51.891us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
		lc_ctrl_tl_intg_err	4.440s	119.318us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.440s	119.318us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.500s	1.379ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.470s	2.238ms	50	50	100.00
		lc_ctrl_sec_cm	38.870s	800.640us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.500s	435.934us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.540s	1.067ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.940s	4.139ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.110s	569.573us	36	50	72.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.110s	569.573us	36	50	72.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	18.590s	2.466ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.930s	1.089ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.930s	1.089ms	50	50	100.00
V2S		TOTAL			161	175	92.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.808h	32.430ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			982	1030	95.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	97.99	95.68	93.38	100.00	98.55	98.51	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.32079504007999945278924996836186742425118801598153332888038854136759265930189
    Line 19510, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 77449138197 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 77449138197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.81296990301051679675479316531431595572221472118580168141189763570395571866977
    Line 3925, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17836708114 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17836708114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 14 failures:
- Test lc_ctrl_sec_mubi has 14 failures.
  - 0.lc_ctrl_sec_mubi.79735804764438844664816383724280985592015227773196753916872045993847401615598
    Line 1042, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @  65804853 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  65804853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_sec_mubi.34287046936455982175699445361559860044390882348801254012219344486783055619433
    Line 456, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @  24603388 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  24603388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.2741322660424127364162368190671500562199118382097098802155467903186950138453
    Line 33298, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10009731659 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 10009731659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.lc_ctrl_stress_all_with_rand_reset.75573185342965283223374465111478593830604012922500637674690722013914457935753
    Line 9990, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21205365400 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:15000
  UVM_INFO @ 21205365400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 11.lc_ctrl_stress_all_with_rand_reset.81212523148632912251046203433520994433343255973994408071324412133488505490000
    Line 46566, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 193113126861 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 193113126861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.lc_ctrl_stress_all_with_rand_reset.76905503116659419081194565477316489536560290285263557558074408863008668863192
    Line 30195, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137066791487 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 137066791487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 23.lc_ctrl_stress_all_with_rand_reset.49741928734049616214833111530775477231760505878324217123924371927963989736367
    Line 94055, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 24.lc_ctrl_stress_all.64691334156620556369222528616038947151314828649333057306389103682670148541156
    Line 8332, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 8591515029 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 8591515029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.lc_ctrl_stress_all_with_rand_reset.109365855842891783302562374598398697697127143056908864742407662247331800191543
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0b007b8c-27d9-4f3b-8131-52b6c70332fd
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`