LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.980s	188.772us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	18.847us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	58.293us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.560s	77.908us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	35.584us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.710s	45.520us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	58.293us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	35.584us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.230s	90.001us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.550s	335.480us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	11.080us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.330s	184.456us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.480s	3.602ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_prog_failure	4.330s	184.456us	50	50	100.00
		lc_ctrl_errors	21.480s	3.602ms	50	50	100.00
		lc_ctrl_security_escalation	15.520s	1.526ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.882m	14.354ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.010s	632.177us	20	20	100.00
		lc_ctrl_jtag_errors	1.520m	14.117ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.020s	1.734ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	41.390s	4.355ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.010s	632.177us	20	20	100.00
		lc_ctrl_jtag_errors	1.520m	14.117ms	20	20	100.00
		lc_ctrl_jtag_access	27.800s	1.172ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.430s	10.039ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.930s	778.085us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.220s	150.758us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.100s	25.461ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.230s	2.433ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.050s	46.191us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.430s	931.042us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.430s	63.765us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.310m	13.415ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.350s	91.223us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.250m	28.084ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.420s	32.584us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.910s	133.959us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.910s	133.959us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	18.847us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	58.293us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	35.584us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	262.373us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	18.847us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	58.293us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	35.584us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	262.373us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
		lc_ctrl_tl_intg_err	4.840s	2.044ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.840s	2.044ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.550s	335.480us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.770s	1.472ms	50	50	100.00
		lc_ctrl_sec_cm	39.880s	905.624us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.520s	1.526ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.230s	90.001us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	41.390s	4.355ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.870s	1.467ms	39	50	78.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.870s	1.467ms	39	50	78.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.540s	3.335ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.990s	4.672ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.990s	4.672ms	50	50	100.00
V2S		TOTAL			164	175	93.71
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	24.020m	43.347ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			987	1030	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	97.99	95.77	93.40	100.00	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.10852099344037813863150469357873105087617090577451408905630816995696978949444
      Line 28073, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29115036808 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29115036808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.61360757776112311101081983169279691155801752252356027792601002636506476932033
      Line 13636, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7232723383 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7232723383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 11 failures:
  • Test lc_ctrl_sec_mubi has 11 failures.

    • 5.lc_ctrl_sec_mubi.58073464994501776198511423830825738291499849876520318742872519150117066401033
      Line 2112, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 486237351 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 486237351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.lc_ctrl_sec_mubi.80182969905428004274677771184302931891267419284459913149726739891420624895504
      Line 1500, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 314111597 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 314111597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 6 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 6 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.64109150700147117485553246902956558827625771792968841839401820588964764807899
      Line 10475, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72262470146 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 72262470146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.33686579398794455687706329861873254035551543270413001901733913324684841575308
      Line 45156, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 76980723905 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 76980723905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.6227877353863897012661856815595128562738062009921575459732771029003711902811
      Line 19879, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30648411429 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 30648411429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.15_09.28.47
• 2024.07.14_08.44.43
• 2024.07.13_08.23.58
• 2024.07.12_09.10.35
• 2024.07.11_10.36.05
• 2024.07.10_10.43.37
• 2024.07.08_10.13.48