LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.190s	144.137us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	30.831us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	18.404us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.930s	314.281us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.710s	129.488us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.160s	108.622us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	18.404us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	129.488us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.050s	348.375us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.170s	1.543ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	12.194us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.650s	1.559ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.660s	2.915ms	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_prog_failure	4.650s	1.559ms	50	50	100.00
		lc_ctrl_errors	26.660s	2.915ms	48	50	96.00
		lc_ctrl_security_escalation	14.700s	419.517us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.478m	2.870ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.610s	660.942us	20	20	100.00
		lc_ctrl_jtag_errors	1.620m	7.133ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.780s	1.242ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.220s	788.525us	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.610s	660.942us	20	20	100.00
		lc_ctrl_jtag_errors	1.620m	7.133ms	20	20	100.00
		lc_ctrl_jtag_access	27.830s	6.412ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	43.140s	1.677ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.000s	2.415ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.360s	118.978us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	56.880s	10.523ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.460s	1.243ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.510s	45.382us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.970s	177.643us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.790s	89.602us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.220s	9.271ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.850s	26.660us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.324m	43.015ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.910s	361.877us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.750s	111.695us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.750s	111.695us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	30.831us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	18.404us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	129.488us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	177.432us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	30.831us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	18.404us	20	20	100.00
		lc_ctrl_csr_aliasing	1.710s	129.488us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	177.432us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
		lc_ctrl_tl_intg_err	3.960s	936.781us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.960s	936.781us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.170s	1.543ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.280s	1.552ms	50	50	100.00
		lc_ctrl_sec_cm	36.020s	219.555us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.700s	419.517us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.050s	348.375us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.220s	788.525us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.650s	3.217ms	35	50	70.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.650s	3.217ms	35	50	70.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.870s	1.286ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.960s	1.236ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.960s	1.236ms	50	50	100.00
V2S		TOTAL			160	175	91.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	47.588m	235.809ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			982	1030	95.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.96	97.99	96.13	93.40	97.67	98.55	98.51	96.47

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 20 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.24427762453863201596804173920026848769100941850405132437113485189580152155259
    Line 8962, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12365402236 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12365402236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.43414632704776641308624007060252080576671507415015401870539103443086099692791
    Line 372, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 166172938 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 166172938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 15 failures:
- Test lc_ctrl_sec_mubi has 15 failures.
  - 3.lc_ctrl_sec_mubi.68923572272402261436655143261606961407603487036198822445754342689063268430512
    Line 544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @  21608778 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  21608778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.lc_ctrl_sec_mubi.21871766381862913873330010872822890957900743924459312696978327372056862705018
    Line 4096, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 5371438522 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5371438522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 6 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 6 failures.
  - 6.lc_ctrl_stress_all_with_rand_reset.42919745621349472714688062270380436303376292883783903893376217918711011219642
    Line 8825, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11813239111 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 11813239111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.lc_ctrl_stress_all_with_rand_reset.8175692102738296414288290114157344145509080173591473104879668514625971988868
    Line 12622, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6882971852 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 6882971852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.lc_ctrl_stress_all_with_rand_reset.111994681212556340782169037588304359593419039120511842368092518474536825753695
    Line 2881, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2130404891 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2130404891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_errors has 1 failures.
  - 36.lc_ctrl_errors.97231150983793281943862233468973515772909488904403815587832842904476348940480
    Line 1648, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @  99107727 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  99107727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.57958426760378791207884709194943563275238524599120221398818213326843624856605
    Line 66445, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.lc_ctrl_stress_all_with_rand_reset.9228603792054008126199230434029193281605501768243682938177995191107087137817
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:79c65fed-a6c3-4f68-9bb0-1e8b3517b85f
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 11.lc_ctrl_stress_all_with_rand_reset.23997367444101728183096147525061890010789060834594349790416225607982375450297
    Line 11114, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13796891921 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 13796891921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_errors has 1 failures.
  - 20.lc_ctrl_errors.94347700340051450547561139484181384358286854179484953256580414106041261006269
    Line 1123, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @ 330098669 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 330098669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.lc_ctrl_stress_all_with_rand_reset.110258580781590607340075736940342763537914469933793685001236137442325626485585
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e47af941-93b1-47ce-8d2f-2fd39216046a
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `aad711e1bc`