LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	14.200s	1.005ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	87.098us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	31.867us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.680s	75.876us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.750s	272.693us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.290s	119.684us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	31.867us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	272.693us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.020s	147.870us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.720s	320.127us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	12.766us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.610s	355.721us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.020s	1.101ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_prog_failure	6.610s	355.721us	50	50	100.00
		lc_ctrl_errors	22.020s	1.101ms	50	50	100.00
		lc_ctrl_security_escalation	17.950s	488.462us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.310m	9.205ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.920s	475.104us	20	20	100.00
		lc_ctrl_jtag_errors	2.563m	23.586ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.720s	1.852ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.390s	1.601ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.920s	475.104us	20	20	100.00
		lc_ctrl_jtag_errors	2.563m	23.586ms	20	20	100.00
		lc_ctrl_jtag_access	16.580s	3.608ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.550s	7.355ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.470s	164.497us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.310s	328.614us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	54.800s	5.080ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.840s	1.387ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.150s	256.047us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.940s	876.998us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.870s	411.669us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	38.630s	9.144ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	26.445us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.729m	178.672ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	28.465us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.830s	114.759us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.830s	114.759us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	87.098us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	31.867us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	272.693us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.280s	54.850us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	87.098us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	31.867us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	272.693us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.280s	54.850us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
		lc_ctrl_tl_intg_err	4.120s	465.076us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.120s	465.076us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.720s	320.127us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.300s	1.513ms	50	50	100.00
		lc_ctrl_sec_cm	38.120s	440.440us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.950s	488.462us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.020s	147.870us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.390s	1.601ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.970s	798.433us	43	50	86.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.970s	798.433us	43	50	86.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.040s	2.588ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.610s	415.402us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.610s	415.402us	50	50	100.00
V2S		TOTAL			168	175	96.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.193h	81.323ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	97.99	95.41	93.40	100.00	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.14418790611371329184250232970491136133963356832246215272872980316774442506680
      Line 378, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 932856757 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 932856757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.79454136316133179950027829556706514181919883226943352163852892153843917375833
      Line 15753, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 112675884265 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 112675884265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 7 failures:

  • Test lc_ctrl_sec_mubi has 7 failures.

    • 2.lc_ctrl_sec_mubi.65425618597708221395975372440476462603028280817537933581241253063617061763747
      Line 640, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  21021358 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  21021358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_sec_mubi.17459136446142966704525260727993846482950795399062378864782766124396900285237
      Line 4020, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 1035220341 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1035220341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.71733143860554381027351121685488312243522282171073390301781572444896438518293
      Line 60874, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 11.lc_ctrl_stress_all_with_rand_reset.91214824141986074862785737570461037929412361104225650970377200544746009851529
      Line 29455, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.40140673482783926368683411086731337708286083180740690746418229059483960419626
      Line 3373, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 524161472 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked2
        UVM_INFO @ 524161472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.110484558714920899624573093198800750169202795715795552213500175804388199227703
      Line 11110, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30611160577 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked6
        UVM_INFO @ 30611160577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.17_09.33.20
• 2024.07.16_09.39.46
• 2024.07.15_09.28.47
• 2024.07.14_08.44.43
• 2024.07.13_08.23.58
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• 2024.07.11_10.36.05