LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.170s	780.259us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	27.526us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	20.851us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.960s	391.389us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.340s	42.391us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.300s	33.370us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	20.851us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	42.391us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.370s	191.847us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.760s	388.875us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	13.426us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.760s	109.715us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.050s	479.179us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_prog_failure	4.760s	109.715us	50	50	100.00
		lc_ctrl_errors	21.050s	479.179us	50	50	100.00
		lc_ctrl_security_escalation	17.430s	1.850ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.730m	13.951ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.380s	1.572ms	20	20	100.00
		lc_ctrl_jtag_errors	1.095m	8.359ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.540s	318.308us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.660s	2.382ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.380s	1.572ms	20	20	100.00
		lc_ctrl_jtag_errors	1.095m	8.359ms	20	20	100.00
		lc_ctrl_jtag_access	28.870s	1.250ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.970s	1.215ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.530s	463.474us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.230s	177.237us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	19.480s	981.696us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.950s	948.349us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.990s	42.974us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.730s	245.972us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.220s	251.947us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	39.950s	3.396ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.290s	30.436us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	16.096m	122.434ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.420s	168.715us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.050s	161.364us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.050s	161.364us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	27.526us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	20.851us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	42.391us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	161.930us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	27.526us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	20.851us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	42.391us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	161.930us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
		lc_ctrl_tl_intg_err	4.580s	123.989us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.580s	123.989us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.760s	388.875us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	33.100s	272.629us	50	50	100.00
		lc_ctrl_sec_cm	38.380s	234.263us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.430s	1.850ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.370s	191.847us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.660s	2.382ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.090s	2.385ms	45	50	90.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.090s	2.385ms	45	50	90.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.790s	3.750ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.770s	454.642us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.770s	454.642us	50	50	100.00
V2S		TOTAL			170	175	97.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.521h	160.881ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.90	97.99	95.68	93.40	97.67	98.55	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.105393350986072910916566032033060293145501349021657636610002790074861180342520
      Line 6879, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46408749717 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 46408749717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.64764931140854988591742706109187159351414240715520664453561520665435912415582
      Line 28201, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14301614410 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14301614410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 5 failures:

  • Test lc_ctrl_sec_mubi has 5 failures.

    • 10.lc_ctrl_sec_mubi.38918810971118992054363943059215061016737801402924538342675387500135635629379
      Line 3284, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 467725982 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 467725982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_sec_mubi.99824616050360864919181419299424593986031283823419149051318028186956459050284
      Line 554, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  88117476 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  88117476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.35935666418341795004001027763731399619433665144773249547178200183534637927613
      Line 22049, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 97632568917 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 97632568917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.82916767545936094370409614383090902299352969735129307401832590930565266393528
      Line 32492, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.48008329226164512491022140689441332927505418225513842421731501079634393094343
      Line 11368, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15105728048 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 15105728048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.18_09.22.54
• 2024.07.17_09.33.20
• 2024.07.16_09.39.46
• 2024.07.15_09.28.47
• 2024.07.14_08.44.43
• 2024.07.13_08.23.58
• 2024.07.12_09.10.35