LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.590s	224.832us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	54.909us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.080s	16.696us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.940s	321.265us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.300s	264.038us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.420s	64.358us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.080s	16.696us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	264.038us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.020s	69.015us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.360s	381.282us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	11.324us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.790s	135.642us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.590s	1.202ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_prog_failure	5.790s	135.642us	50	50	100.00
		lc_ctrl_errors	25.590s	1.202ms	50	50	100.00
		lc_ctrl_security_escalation	18.730s	530.322us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.234m	1.534ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.060s	971.229us	20	20	100.00
		lc_ctrl_jtag_errors	1.963m	8.397ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.010s	755.214us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.930s	21.047ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.060s	971.229us	20	20	100.00
		lc_ctrl_jtag_errors	1.963m	8.397ms	20	20	100.00
		lc_ctrl_jtag_access	22.030s	886.550us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.490s	1.178ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.450s	3.617ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.330s	123.728us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	33.050s	3.031ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.570s	1.600ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.880s	167.068us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.100s	925.903us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.210s	235.568us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.020s	1.346ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.620s	30.007us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	13.487m	160.512ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.460s	235.613us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.990s	567.013us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.990s	567.013us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	54.909us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	16.696us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	264.038us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	166.799us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	54.909us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	16.696us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	264.038us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	166.799us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
		lc_ctrl_tl_intg_err	3.960s	436.798us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.960s	436.798us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.360s	381.282us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.920s	1.055ms	50	50	100.00
		lc_ctrl_sec_cm	41.310s	428.916us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.730s	530.322us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.020s	69.015us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.930s	21.047ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.540s	1.218ms	40	50	80.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.540s	1.218ms	40	50	80.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.000s	2.957ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.750s	833.219us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.750s	833.219us	50	50	100.00
V2S		TOTAL			165	175	94.29
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	34.398m	25.774ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			989	1030	96.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.99	95.77	93.40	97.67	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.63732800460846270458369737284429752329017606331715109274840136360412717939606
      Line 7822, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35867059530 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 35867059530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.59753585442034137124020191555558059157074532436549572123036365692865398431804
      Line 31362, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28811598313 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28811598313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 10 failures:

  • Test lc_ctrl_sec_mubi has 10 failures.

    • 2.lc_ctrl_sec_mubi.90843105462839243939250606269442480123821574568823680218974386461351630864848
      Line 1190, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  80123142 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  80123142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.lc_ctrl_sec_mubi.12224223181561903864406654381764567852522570555276014829325941589986495020152
      Line 412, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @   7569080 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @   7569080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.14098643805431695346218145268842836870083888057392980632273570136762520968592
      Line 48313, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58926553449 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 58926553449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.lc_ctrl_stress_all_with_rand_reset.40869347511021149009406311689542535621499951616858708407964891593586315845876
      Line 36761, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66096196569 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 66096196569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.11707680990359817039937720321384394395947692917811940112788943301865652386739
      Line 10747, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12399458976 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 12399458976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.47332023866096836367009238913880033323617051728833492603871577674625256776018
      Line 8540, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6236760635 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 6236760635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.81643671931015205556879248232938136825384889506421791409204976340663350176416
      Line 26674, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28608795251 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 28608795251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.lc_ctrl_stress_all_with_rand_reset.89135603986292244965504096451205762882794527829730114992284786796750402090955
      Line 3044, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2786289143 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2786289143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 30.lc_ctrl_volatile_unlock_smoke.85900786998767928995736717673680995334054427362838758357993114174521717562702
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 151429204 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x6afaca04, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 151429204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.90893007456388172854365351398773124884737031507770224342588979819468269820263
      Line 35948, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

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