LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.070s	128.476us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.350s	19.671us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	53.319us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.270s	376.496us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.440s	20.607us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.110s	172.616us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	53.319us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	20.607us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.180s	223.759us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.020s	6.501ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	12.197us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.200s	126.090us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.560s	721.335us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_prog_failure	5.200s	126.090us	50	50	100.00
		lc_ctrl_errors	26.560s	721.335us	50	50	100.00
		lc_ctrl_security_escalation	18.820s	504.339us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.660m	24.817ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.720s	1.668ms	20	20	100.00
		lc_ctrl_jtag_errors	1.923m	9.171ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.420s	584.436us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.200s	4.433ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.720s	1.668ms	20	20	100.00
		lc_ctrl_jtag_errors	1.923m	9.171ms	20	20	100.00
		lc_ctrl_jtag_access	20.110s	1.719ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.160s	14.469ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.310s	202.811us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.710s	96.335us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.100s	6.008ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.230s	1.010ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.580s	22.179us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.690s	200.798us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.250s	112.149us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.210s	1.440ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.440s	17.743us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.205m	67.662ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.700s	228.228us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.200s	136.747us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.200s	136.747us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.350s	19.671us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	53.319us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	20.607us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	37.809us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.350s	19.671us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	53.319us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	20.607us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	37.809us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
		lc_ctrl_tl_intg_err	6.050s	221.404us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.050s	221.404us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.020s	6.501ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.610s	568.742us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	2.323ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.820s	504.339us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.180s	223.759us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.200s	4.433ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.340s	1.486ms	35	50	70.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.340s	1.486ms	35	50	70.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.760s	1.020ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.810s	2.491ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.810s	2.491ms	50	50	100.00
V2S		TOTAL			160	175	91.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.982h	8.292ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			977	1030	94.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.99	96.22	93.40	100.00	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.90291194216054968197565681410526552097323001788521113542712270342436465779783
      Line 3240, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7193422327 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7193422327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.96780783054827113765076628849938900995247601362299819835012773554398368295641
      Line 29282, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 154550889091 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 154550889091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 15 failures:

  • Test lc_ctrl_sec_mubi has 15 failures.

    • 0.lc_ctrl_sec_mubi.29555892235458793293926423405874700070521478919014789764702272209528690118132
      Line 3586, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 1694217494 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1694217494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_sec_mubi.106317789646992856831290233463365823626028242306003400329149672675514601911635
      Line 1712, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 660261815 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 660261815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.40916584998701414442085481776402284191397381316497023809826558524215615577416
      Line 37560, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 17.lc_ctrl_stress_all_with_rand_reset.19646868864013359733903334373822714378996731692603006719112643383411103874504
      Line 36888, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 0.lc_ctrl_stress_all.3441565946827922963462601130250544194671110060123649289466386593665742411066
      Line 10418, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 18965379015 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 18965379015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 38.lc_ctrl_stress_all.36183309823556594088695357966278204169486266463165668466012914410772792729778
      Line 10388, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 29789468074 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 29789468074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.49318008008858961119876319632505358716792336041918013551289153426319472514965
      Line 26391, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32545617412 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 32545617412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.63496019026110235729263262106728733979024397831083458687249676140199504826529
      Line 13591, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23618912824 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 23618912824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.lc_ctrl_stress_all_with_rand_reset.56859656864124377166253771643250580614443944188821180873200851355059762740640
      Line 8819, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37729755735 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 37729755735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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