LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.060s	578.607us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	20.548us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	17.474us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.020s	403.142us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.380s	18.121us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.310s	29.382us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	17.474us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	18.121us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.160s	70.948us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.360s	544.406us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.050s	12.377us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.450s	567.425us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.910s	2.042ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_prog_failure	5.450s	567.425us	50	50	100.00
		lc_ctrl_errors	20.910s	2.042ms	49	50	98.00
		lc_ctrl_security_escalation	16.700s	894.672us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.986m	8.322ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.300s	1.714ms	20	20	100.00
		lc_ctrl_jtag_errors	1.341m	8.221ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.750s	1.518ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.450s	3.516ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.300s	1.714ms	20	20	100.00
		lc_ctrl_jtag_errors	1.341m	8.221ms	20	20	100.00
		lc_ctrl_jtag_access	20.600s	8.350ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.690s	5.442ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.000s	390.082us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.620s	81.681us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	24.230s	4.403ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.150s	952.675us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.340s	100.802us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.240s	473.732us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.850s	417.341us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	56.070s	10.005ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.230s	102.888us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.275m	18.135ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	32.733us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.010s	124.331us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.010s	124.331us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	20.548us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	17.474us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	18.121us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	240.884us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	20.548us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	17.474us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	18.121us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	240.884us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
		lc_ctrl_tl_intg_err	3.810s	356.954us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.810s	356.954us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.360s	544.406us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.080s	355.551us	50	50	100.00
		lc_ctrl_sec_cm	42.800s	271.852us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.700s	894.672us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.160s	70.948us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.450s	3.516ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.900s	2.953ms	42	50	84.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.900s	2.953ms	42	50	84.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.040s	780.439us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.750s	4.805ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.750s	4.805ms	50	50	100.00
V2S		TOTAL			167	175	95.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.256h	200.223ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			990	1030	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.99	95.95	93.40	100.00	98.55	98.51	96.47

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.114961479307771147171746502685792714305670950500038842200555421498351116672089
    Line 29025, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25768633478 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25768633478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.77897313854818970949032637810828601148806361801929793856109983650726636027637
    Line 19194, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42702052735 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42702052735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 8 failures:
- Test lc_ctrl_sec_mubi has 8 failures.
  - 3.lc_ctrl_sec_mubi.81543550851593858209262506225571591389805739929321272264744408134815048981267
    Line 992, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @  99861606 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  99861606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.lc_ctrl_sec_mubi.58006316046956188173076417873491088835978352294951536370825374180235285993179
    Line 678, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 556463538 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 556463538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 37.lc_ctrl_stress_all_with_rand_reset.64958175496779828877385600071251616981502233262083726241240844691447267154083
    Line 44095, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 41.lc_ctrl_stress_all_with_rand_reset.86288431173087329231611346923733546392607687136613362523295033908671557508557
    Line 63620, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 18.lc_ctrl_stress_all_with_rand_reset.13909425842847520694729619893174548237620734490677161490761918501419086888146
    Line 11127, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19720916977 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 19720916977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.lc_ctrl_stress_all_with_rand_reset.46085390860396742300730919522444068148955559969716736487258299203970357428538
    Line 46472, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 60146411527 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 60146411527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 26.lc_ctrl_stress_all_with_rand_reset.51686174933305337478967292611622855398095644588718729017908835471059151355260
    Line 26639, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32822896781 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 32822896781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.lc_ctrl_stress_all_with_rand_reset.48345477473270200086321737065668839798732704006657845967092640461579854515284
    Line 35094, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 60308986285 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 60308986285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_errors has 1 failures.
  - 1.lc_ctrl_errors.28771516590319427363773987283429257110686601411781178602269261437790513847389
    Line 1511, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @ 450491450 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 450491450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:
- Test lc_ctrl_jtag_priority has 1 failures.
  - 2.lc_ctrl_jtag_priority.30333919340613366297701876995833720230838934446736906486701831476178060387184
    Line 682, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_priority/latest/run.log
```
  UVM_FATAL @ 10005106949 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
  UVM_INFO @ 10005106949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`