LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.210s	146.002us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	48.816us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	16.416us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.960s	92.088us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.730s	38.716us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.130s	45.610us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	16.416us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	38.716us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.070s	370.887us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.630s	1.753ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	13.467us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.510s	428.339us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.330s	682.518us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_prog_failure	4.510s	428.339us	50	50	100.00
		lc_ctrl_errors	27.330s	682.518us	50	50	100.00
		lc_ctrl_security_escalation	15.330s	5.227ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.918m	31.032ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.130s	841.521us	20	20	100.00
		lc_ctrl_jtag_errors	1.533m	12.802ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.380s	5.165ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.360s	11.371ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.130s	841.521us	20	20	100.00
		lc_ctrl_jtag_errors	1.533m	12.802ms	20	20	100.00
		lc_ctrl_jtag_access	17.730s	947.015us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.240s	8.808ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.650s	1.202ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.220s	666.866us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.890s	4.669ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.730s	7.790ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.990s	97.030us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.590s	258.612us	10	10	100.00
		lc_ctrl_jtag_alert_test	4.450s	1.929ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	26.680s	1.208ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.320s	19.078us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	10.933m	78.656ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.610s	44.841us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.330s	159.859us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.330s	159.859us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	48.816us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.416us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	38.716us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	36.960us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	48.816us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.416us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	38.716us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.820s	36.960us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
		lc_ctrl_tl_intg_err	4.280s	144.152us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.280s	144.152us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.630s	1.753ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.410s	720.969us	50	50	100.00
		lc_ctrl_sec_cm	37.460s	907.568us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.330s	5.227ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.070s	370.887us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.360s	11.371ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.780s	571.184us	37	50	74.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.780s	571.184us	37	50	74.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.470s	874.706us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.220s	3.437ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.220s	3.437ms	50	50	100.00
V2S		TOTAL			162	175	92.57
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.262h	101.361ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			987	1030	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.14	97.99	95.41	93.40	100.00	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.105363764627747873935806903837169833282736596649864013121044609099492889470233
      Line 13038, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37187084137 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 37187084137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.76162921052554528307820189920094485053564620508047276656447450210842141404922
      Line 26589, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37380008505 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 37380008505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 13 failures:

  • Test lc_ctrl_sec_mubi has 13 failures.

    • 1.lc_ctrl_sec_mubi.94720460854014115924368526822915269855571776989431784486236348631166510387171
      Line 878, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  36260992 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  36260992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_sec_mubi.106104658630420497155926641662088038802976769243451017302306335572982546116659
      Line 770, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  61653761 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  61653761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.32326563550245630353293275402143375082496455799508208756387239135531321541023
      Line 26611, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23005527519 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 23005527519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.lc_ctrl_stress_all_with_rand_reset.9529142476510608461972301616181382107001486160391304266256977929616005564287
      Line 17780, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52666891942 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 52666891942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 0.lc_ctrl_volatile_unlock_smoke.92097354359838934340498791735759026507498968933531161838398882630139119078351
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 133260830 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x9f31f004, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 133260830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.94216036058342060782143432896765291073486244752042541621490861085009881578446
      Line 29127, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.22_08.45.57
• 2024.07.21_08.26.08
• 2024.07.20_09.49.24
• 2024.07.19_08.51.26
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