LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.700s	868.322us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	40.291us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	34.355us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.880s	53.456us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.770s	144.313us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.890s	103.444us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	34.355us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	144.313us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.510s	121.291us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.170s	382.146us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	12.018us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.320s	103.458us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.060s	668.793us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_prog_failure	4.320s	103.458us	50	50	100.00
		lc_ctrl_errors	26.060s	668.793us	50	50	100.00
		lc_ctrl_security_escalation	17.400s	546.951us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.605m	12.736ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.250s	854.804us	20	20	100.00
		lc_ctrl_jtag_errors	1.477m	2.886ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.370s	2.066ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.390s	932.760us	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.250s	854.804us	20	20	100.00
		lc_ctrl_jtag_errors	1.477m	2.886ms	20	20	100.00
		lc_ctrl_jtag_access	27.460s	7.336ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	28.670s	2.926ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.760s	999.528us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.420s	78.404us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.270s	9.326ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.360s	2.303ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	90.511us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.210s	302.152us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.020s	241.428us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.200s	1.530ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	54.467us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.878m	22.347ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.340s	29.693us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.450s	110.870us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.450s	110.870us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	40.291us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	34.355us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	144.313us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	76.789us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	40.291us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	34.355us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	144.313us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	76.789us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
		lc_ctrl_tl_intg_err	4.290s	216.785us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.290s	216.785us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.170s	382.146us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.630s	1.457ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	431.650us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.400s	546.951us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.510s	121.291us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.390s	932.760us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.880s	2.344ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.880s	2.344ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.070s	746.925us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.910s	9.427ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.910s	9.427ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.367h	201.771ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.99	95.77	93.40	100.00	98.55	98.51	96.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.28926870696657916531594776569521915266280838262461649288843398055127883215649
      Line 29892, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 331856661427 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 331856661427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.66903589272613926841074012569171076038232842106661716179878783352402044479702
      Line 30954, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 324207288280 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 324207288280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.74490976349284233342282197132224681639323645576528271141737287597823091980594
      Line 37066, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 62759256907 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 62759256907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.lc_ctrl_stress_all_with_rand_reset.38676332662698235250780940486258797454363109589859219315136485256108577741530
      Line 18236, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70726927185 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 70726927185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.73278922316351166544223781562539318316803202985517161337523561486681483039191
      Line 71753, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.45111304071017916239309112444567475139212883541421768955880952420469244326821
      Line 19954, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35077953929 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 35077953929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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