LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.130s	1.649ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	20.877us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.080s	20.836us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.130s	91.979us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.650s	32.298us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.800s	103.283us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.080s	20.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	32.298us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.650s	473.586us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	15.920s	948.158us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	13.216us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.250s	92.097us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.070s	11.448ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_prog_failure	4.250s	92.097us	50	50	100.00
		lc_ctrl_errors	28.070s	11.448ms	50	50	100.00
		lc_ctrl_security_escalation	14.930s	1.412ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.310m	9.470ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.030s	3.844ms	20	20	100.00
		lc_ctrl_jtag_errors	1.692m	13.860ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.280s	2.568ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.640s	1.669ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.030s	3.844ms	20	20	100.00
		lc_ctrl_jtag_errors	1.692m	13.860ms	20	20	100.00
		lc_ctrl_jtag_access	25.160s	4.238ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.270s	1.192ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.310s	111.084us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.970s	102.274us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.080s	1.528ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.870s	2.897ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.910s	169.127us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.400s	516.978us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.640s	530.595us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	46.260s	5.287ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.370s	43.825us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.529m	31.499ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.500s	32.706us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.570s	122.964us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.570s	122.964us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	20.877us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	20.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	32.298us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	138.950us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	20.877us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	20.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	32.298us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	138.950us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.340s	116.196us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.340s	116.196us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	15.920s	948.158us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	44.640s	341.954us	50	50	100.00
		lc_ctrl_sec_cm	44.170s	1.033ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.930s	1.412ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.650s	473.586us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.640s	1.669ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.080s	2.195ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.080s	2.195ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.000s	2.660ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.730s	1.219ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.730s	1.219ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	31.569m	21.130ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.99	95.59	93.40	100.00	98.55	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.73560649739994038760732146383996984317604143615711311536496839031486353221026
      Line 7838, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5575119764 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5575119764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.69501829442111099248789938765299577913280720428870872654516742648854358931047
      Line 7364, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27569288706 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27569288706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.65005065625752607128038113111977616919331494524901151232033123197303902193256
      Line 62236, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.81018875934229948402606038692204777345351765735078624725262260264054509641781
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:421f7e30-9ad0-42c4-9809-4fb957152549
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:762) [lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.89346247576900477335577625414625352286923442789417016912629126888223153177616
      Line 20192, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 101888229300 ps: (lc_ctrl_errors_vseq.sv:762) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 101888229300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.41907445536504937930957439445177722667837433660209517914490860583897898961364
      Line 12987, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15296856318 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 15296856318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.24_08.13.49
• 2024.07.23_08.46.59
• 2024.07.22_08.45.57
• 2024.07.21_08.26.08
• 2024.07.20_09.49.24
• 2024.07.19_08.51.26
• 2024.07.18_09.22.54