LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.160s	138.421us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	16.979us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	17.505us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.050s	719.479us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.850s	41.125us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.780s	83.201us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	17.505us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	41.125us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.160s	302.829us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.300s	390.701us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	19.565us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.600s	392.920us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.070s	764.392us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_prog_failure	4.600s	392.920us	50	50	100.00
		lc_ctrl_errors	28.070s	764.392us	50	50	100.00
		lc_ctrl_security_escalation	16.250s	397.428us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.261m	4.674ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.150s	732.567us	20	20	100.00
		lc_ctrl_jtag_errors	1.486m	3.232ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.870s	7.609ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.440s	4.757ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.150s	732.567us	20	20	100.00
		lc_ctrl_jtag_errors	1.486m	3.232ms	19	20	95.00
		lc_ctrl_jtag_access	23.290s	1.039ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.140s	14.290ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.200s	481.596us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.400s	355.972us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	32.660s	1.371ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.250s	1.474ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.010s	118.331us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.230s	164.809us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.040s	224.895us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.980s	418.458us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.530s	20.667us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.387m	26.128ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.350s	29.953us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.220s	152.330us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.220s	152.330us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	16.979us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	17.505us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	41.125us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	46.478us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	16.979us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	17.505us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	41.125us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	46.478us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.670s	194.035us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.670s	194.035us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.300s	390.701us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.780s	351.559us	50	50	100.00
		lc_ctrl_sec_cm	34.000s	3.293ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.250s	397.428us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.160s	302.829us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.440s	4.757ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.910s	6.861ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.910s	6.861ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.280s	6.732ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.730s	5.035ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.730s	5.035ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.496h	60.568ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.99	95.77	93.40	97.67	98.55	98.51	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 19 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.53305990185749010172197352968094855868081967921774940614140144605296881947065
    Line 19249, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14357611894 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14357611894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.86642722399564169489138931548867727741908160577661258284277621411581788475206
    Line 37465, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33905979624 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33905979624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 10.lc_ctrl_stress_all_with_rand_reset.108003966093245843760826568696929357660246393281376687176062621193392498254306
    Line 26202, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6714095122 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 6714095122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.lc_ctrl_stress_all_with_rand_reset.92227896173034012382454797871616652848892558025997906302114860849245747878332
    Line 1682, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 818543486 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 818543486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_stress_all has 1 failures.
  - 37.lc_ctrl_stress_all.23395808383273951319462495166204388216603028054059022259477321689733408888247
    Line 4790, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 19060976438 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 19060976438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 8.lc_ctrl_stress_all_with_rand_reset.71068845412317614060251182769352307019560535707785444169613992448643238566198
    Line 43144, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 43.lc_ctrl_stress_all_with_rand_reset.90824173954356024293925673075797973324226175953961584981960033146183397942158
    Line 50529, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_jtag_errors has 1 failures.
  - 18.lc_ctrl_jtag_errors.36808312771731525986068530256160941218811969701260529604209752166294010659229
    Line 886, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_errors/latest/run.log
```
  UVM_ERROR @ 3008138148 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3008138148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:762) [lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 21.lc_ctrl_stress_all_with_rand_reset.79139671736844552863515310646497406713336950455495261320014532669621464961779
    Line 26364, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17492319527 ps: (lc_ctrl_errors_vseq.sv:762) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 17492319527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.lc_ctrl_stress_all_with_rand_reset.41026675771231544461806006503845567574447234545390527066547463416401071000566
    Line 26142, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22408476789 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 22408476789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a47820eb4c`