LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.360s	540.841us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	24.975us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	18.122us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.570s	119.617us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.780s	46.079us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.260s	65.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	18.122us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	46.079us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.760s	166.915us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.850s	940.841us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	14.445us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.460s	744.841us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.160s	6.817ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_prog_failure	6.460s	744.841us	50	50	100.00
		lc_ctrl_errors	23.160s	6.817ms	50	50	100.00
		lc_ctrl_security_escalation	20.160s	651.994us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.004m	12.971ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.250s	774.827us	20	20	100.00
		lc_ctrl_jtag_errors	2.508m	22.748ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.050s	2.729ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.740s	8.841ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.250s	774.827us	20	20	100.00
		lc_ctrl_jtag_errors	2.508m	22.748ms	20	20	100.00
		lc_ctrl_jtag_access	26.110s	2.261ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	42.310s	1.518ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.490s	1.617ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.920s	142.796us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	53.240s	2.995ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.750s	3.903ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.040s	50.324us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.360s	1.915ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.720s	306.991us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.840s	632.564us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	20.759us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.671m	51.333ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.360s	119.835us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.670s	493.407us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.670s	493.407us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	24.975us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	18.122us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	46.079us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	93.569us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	24.975us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	18.122us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	46.079us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	93.569us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
		lc_ctrl_tl_intg_err	5.400s	317.024us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.400s	317.024us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.850s	940.841us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.640s	339.364us	50	50	100.00
		lc_ctrl_sec_cm	39.180s	941.327us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.160s	651.994us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.760s	166.915us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.740s	8.841ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.220s	3.100ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.220s	3.100ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.660s	832.926us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.780s	2.723ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.780s	2.723ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.372h	71.146ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1008	1030	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.99	95.77	93.40	100.00	98.55	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.65533556772026592801584938755954366914193175374902004340142568650947300981564
      Line 18680, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57873768242 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 57873768242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.95281637550962806385730100291213327464658905928241260621503655678931065400308
      Line 7700, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30766887516 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 30766887516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.27030732937656098123509095879632711313501128919878927818754806032198124876254
      Line 46229, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.83170836796898793510771334419897400831754888390278447201655646602709910456703
      Line 38743, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22684460990 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 22684460990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.57628202084529232700564286800313036440235371638061512756905537266454343925035
      Line 9241, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58100423673 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 58100423673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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