LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.500s	184.566us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.160s	20.500us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.060s	13.647us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.840s	81.184us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.180s	72.497us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.050s	63.910us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.060s	13.647us	20	20	100.00
		lc_ctrl_csr_aliasing	1.180s	72.497us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.540s	322.665us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.870s	628.165us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	12.365us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.580s	133.669us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.470s	841.821us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_prog_failure	5.580s	133.669us	50	50	100.00
		lc_ctrl_errors	28.470s	841.821us	50	50	100.00
		lc_ctrl_security_escalation	15.310s	479.908us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.166m	18.798ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.620s	911.580us	20	20	100.00
		lc_ctrl_jtag_errors	1.635m	7.159ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.660s	2.569ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.540s	3.970ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.620s	911.580us	20	20	100.00
		lc_ctrl_jtag_errors	1.635m	7.159ms	19	20	95.00
		lc_ctrl_jtag_access	27.260s	5.185ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	28.300s	1.016ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.460s	1.966ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.670s	212.521us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	17.670s	1.946ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.600s	1.070ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.760s	139.810us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.260s	179.294us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.330s	234.179us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.040s	5.153ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.390s	45.179us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.312m	187.355ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.350s	108.953us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.070s	94.530us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.070s	94.530us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.160s	20.500us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	13.647us	20	20	100.00
		lc_ctrl_csr_aliasing	1.180s	72.497us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	88.880us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.160s	20.500us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	13.647us	20	20	100.00
		lc_ctrl_csr_aliasing	1.180s	72.497us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	88.880us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
		lc_ctrl_tl_intg_err	4.180s	442.461us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.180s	442.461us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.870s	628.165us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.970s	1.525ms	50	50	100.00
		lc_ctrl_sec_cm	38.360s	234.779us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.310s	479.908us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.540s	322.665us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.540s	3.970ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.960s	2.849ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.960s	2.849ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.570s	970.185us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.580s	592.986us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.580s	592.986us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.441h	63.211ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.99	95.77	93.40	100.00	98.55	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 16 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.59597952429223367084452598013989845964621202954677668053358613272929688987589
      Line 19788, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 82008686480 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 82008686480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.92035091000852349522439312591720115944151341029913927486406735472672473400544
      Line 8639, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6900041302 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6900041302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 0.lc_ctrl_jtag_errors.115453996257771692851536923641156694010514010710744272527311816858293762908076
      Line 1256, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 5918065842 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 5918065842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.18478745596399714830842341124700573754488785676426046725035736158789768726104
      Line 13029, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4772193127 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4772193127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 3.lc_ctrl_stress_all.48934013580333478362498914216307185348094901411851303781410761943969082811570
      Line 967, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @  99525002 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  99525002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.15526354505881529104886466573396034538978356246323746063046120347264606660038
      Line 16472, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12831445123 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 12831445123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.lc_ctrl_stress_all_with_rand_reset.81231490849986546856319040728534335461847763093966323287798419092367189110866
      Line 749, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1569137182 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 1569137182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.19201021938312056454131580216303082301306598603379405682884816258030225004900
      Line 55520, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 23.lc_ctrl_stress_all_with_rand_reset.50343720696202345849040975313731467775190702317111946738148493382963110282020
      Line 46335, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.25160384501124610812570503521434058356207078597962857832405898192291740420580
      Line 10792, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24905182752 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 24905182752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.27_09.38.49
• 2024.07.26_09.02.00
• 2024.07.25_08.32.56
• 2024.07.24_08.13.49
• 2024.07.23_08.46.59
• 2024.07.22_08.45.57
• 2024.07.21_08.26.08