LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.050s	325.612us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.150s	23.222us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	17.078us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.110s	481.524us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.320s	146.313us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.140s	26.623us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	17.078us	20	20	100.00
		lc_ctrl_csr_aliasing	1.320s	146.313us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.600s	738.723us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.360s	2.359ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	11.171us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.660s	512.695us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.660s	3.274ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_prog_failure	5.660s	512.695us	50	50	100.00
		lc_ctrl_errors	22.660s	3.274ms	50	50	100.00
		lc_ctrl_security_escalation	14.980s	1.653ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.171m	32.702ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.870s	1.092ms	20	20	100.00
		lc_ctrl_jtag_errors	1.719m	3.752ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.480s	2.047ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.620s	5.285ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.870s	1.092ms	20	20	100.00
		lc_ctrl_jtag_errors	1.719m	3.752ms	20	20	100.00
		lc_ctrl_jtag_access	23.020s	989.329us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.830s	2.686ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.250s	110.001us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.820s	139.703us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.060s	2.693ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	27.910s	1.370ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.610s	41.911us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.940s	392.034us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.570s	102.997us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.560s	1.105ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.290s	43.276us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	5.059m	11.234ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.920s	108.102us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.630s	293.755us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.630s	293.755us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.150s	23.222us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.078us	20	20	100.00
		lc_ctrl_csr_aliasing	1.320s	146.313us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	154.707us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.150s	23.222us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.078us	20	20	100.00
		lc_ctrl_csr_aliasing	1.320s	146.313us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	154.707us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
		lc_ctrl_tl_intg_err	4.440s	130.713us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.440s	130.713us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.360s	2.359ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.100s	235.625us	50	50	100.00
		lc_ctrl_sec_cm	38.870s	446.887us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.980s	1.653ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.600s	738.723us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.620s	5.285ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.070s	888.008us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.070s	888.008us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.720s	669.679us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.270s	1.541ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.270s	1.541ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.158h	33.287ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.91	97.99	96.13	93.40	97.67	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 17 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.85393026806839152406816779946136920841685859152455463651691048974817245676784
      Line 12534, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10157719731 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10157719731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.11017845785879704765449942030120662100119156179379693800850957169255281464480
      Line 334, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1287288919 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1287288919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.28138282906084166529857134660678331627399794243312790657816118397330078283450
      Line 45303, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 88208476372 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 88208476372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.lc_ctrl_stress_all_with_rand_reset.2535660238522287795186315615356469163501929585494391839846336068692141355333
      Line 35041, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 110127348709 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 110127348709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.1068221583297409981826869228249244331032767811881237319909361861826484742277
      Line 6840, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 108766143165 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 108766143165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 13.lc_ctrl_stress_all.115092507034255924510663789298975161048226708625337700919800220155085646029833
      Line 3792, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 17870034616 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 17870034616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.26964943047865819556381189925552602283504871770378196955896838036548802718828
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:0f297390-41fa-4ef4-bdb2-484ac3f44339
      

Past Results

• Latest
• 2024.07.28_10.46.59
• 2024.07.27_09.38.49
• 2024.07.26_09.02.00
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