LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.080s	428.512us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.030s	23.871us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	16.777us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.210s	488.047us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.720s	120.106us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.830s	415.932us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	16.777us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	120.106us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.330s	160.762us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.490s	695.619us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	30.434us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.110s	773.914us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.900s	1.109ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_prog_failure	7.110s	773.914us	50	50	100.00
		lc_ctrl_errors	23.900s	1.109ms	49	50	98.00
		lc_ctrl_security_escalation	15.240s	829.769us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.592m	10.538ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.190s	608.563us	20	20	100.00
		lc_ctrl_jtag_errors	2.340m	7.506ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.920s	1.408ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.710s	8.572ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.190s	608.563us	20	20	100.00
		lc_ctrl_jtag_errors	2.340m	7.506ms	20	20	100.00
		lc_ctrl_jtag_access	18.550s	2.704ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.910s	6.290ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.090s	320.590us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.470s	129.286us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.290s	2.068ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.280s	1.537ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.650s	133.410us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.820s	149.720us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.560s	572.492us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	24.310s	2.064ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	20.749us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.876m	31.897ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.500s	34.418us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.270s	138.097us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.270s	138.097us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.030s	23.871us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	16.777us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	120.106us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	50.188us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.030s	23.871us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	16.777us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	120.106us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	50.188us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
		lc_ctrl_tl_intg_err	4.730s	541.042us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.730s	541.042us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.490s	695.619us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.170s	358.355us	50	50	100.00
		lc_ctrl_sec_cm	40.710s	437.033us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.240s	829.769us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.330s	160.762us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.710s	8.572ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.460s	2.828ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.460s	2.828ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.250s	3.143ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.700s	443.786us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.700s	443.786us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	32.761m	25.366ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.99	96.04	93.40	100.00	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.78309669211243862450691393168512896835809884468733849548302366474565262802745
      Line 8592, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29940412589 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29940412589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.79903413254913731341714102900038431443316027126239422251817941144804003228328
      Line 6192, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5042535433 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5042535433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.40552499962686066228414351121422821076274547917896450338602221064240287513633
      Line 3211, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1897017436 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 1897017436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.lc_ctrl_stress_all_with_rand_reset.73543432545993178138903432453766220261102493535693355003943298083929123696624
      Line 7895, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5737908016 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5737908016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.90273483191575439011319805141641003467805734632508769663124813168201269633408
      Line 34085, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 14.lc_ctrl_stress_all_with_rand_reset.33702253231740732280291693928346797925934079770039710494898664220046995997017
      Line 42361, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 26.lc_ctrl_errors.25360083680952979277528015247560708928031413184011447664606536479035412814305
      Line 1597, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 317858116 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 317858116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.29_07.48.21
• 2024.07.28_10.46.59
• 2024.07.27_09.38.49
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