LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.810s	455.705us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	33.827us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	14.678us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.990s	120.691us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.850s	41.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.240s	103.837us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	14.678us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	41.117us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.610s	102.695us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.090s	1.404ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.387us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.580s	508.668us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.330s	709.531us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_prog_failure	4.580s	508.668us	50	50	100.00
		lc_ctrl_errors	26.330s	709.531us	49	50	98.00
		lc_ctrl_security_escalation	15.570s	555.750us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.572m	2.728ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.360s	3.475ms	20	20	100.00
		lc_ctrl_jtag_errors	1.771m	20.612ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.210s	250.269us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.190s	1.996ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.360s	3.475ms	20	20	100.00
		lc_ctrl_jtag_errors	1.771m	20.612ms	20	20	100.00
		lc_ctrl_jtag_access	25.920s	4.331ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.160s	1.145ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.190s	1.039ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.250s	672.412us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.260s	1.523ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.700s	580.404us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.750s	138.192us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.260s	945.359us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.780s	679.522us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.590s	2.698ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.340s	18.185us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.226m	425.822ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.550s	486.848us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.230s	923.197us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.230s	923.197us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	33.827us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	14.678us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	41.117us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	175.099us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	33.827us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	14.678us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	41.117us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	175.099us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
		lc_ctrl_tl_intg_err	6.370s	245.886us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.370s	245.886us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.090s	1.404ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.050s	1.056ms	50	50	100.00
		lc_ctrl_sec_cm	34.400s	463.246us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.570s	555.750us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.610s	102.695us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.190s	1.996ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.230s	4.297ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.230s	4.297ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.870s	771.140us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.600s	863.075us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.600s	863.075us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.257h	37.172ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	97.99	95.59	93.40	100.00	98.55	98.51	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 22 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.21319519882672771570461482119817488897010077680577361875753191560274857378945
    Line 27038, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 236395168648 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 236395168648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.lc_ctrl_stress_all_with_rand_reset.20239831722153308368235028782348336692173676140407297688387484012618545997884
    Line 6545, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18307944264 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18307944264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 12.lc_ctrl_stress_all_with_rand_reset.24299183173640628381765211262826697653151420697046272055239479217298883284192
    Line 50051, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 13.lc_ctrl_stress_all_with_rand_reset.110339041427482766452910518763356560138306198377813967706880668398722086869931
    Line 22278, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.82659211020780700464648686874838591897085196699816853096956380926505727578688
    Line 27054, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30542867376 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 30542867376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_errors has 1 failures.
  - 9.lc_ctrl_errors.106653133129204612689360739798853514136593801375929802658596478751764506948933
    Line 987, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @ 620716199 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 620716199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `fdfa12db04`