LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.770s	664.988us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.290s	39.708us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	45.165us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.960s	101.175us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.660s	127.136us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.910s	88.562us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	45.165us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	127.136us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.920s	102.738us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.830s	1.338ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	13.258us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.660s	561.244us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.460s	2.827ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_prog_failure	5.660s	561.244us	50	50	100.00
		lc_ctrl_errors	25.460s	2.827ms	49	50	98.00
		lc_ctrl_security_escalation	18.480s	5.034ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.692m	16.580ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.170s	2.714ms	20	20	100.00
		lc_ctrl_jtag_errors	2.147m	21.525ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.740s	2.572ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.760s	17.148ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.170s	2.714ms	20	20	100.00
		lc_ctrl_jtag_errors	2.147m	21.525ms	19	20	95.00
		lc_ctrl_jtag_access	18.030s	1.742ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.280s	2.804ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.160s	159.969us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.890s	91.414us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	28.650s	2.366ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.540s	3.923ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.890s	172.393us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.430s	3.056ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.950s	250.985us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.010s	14.153ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	19.369us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.040m	12.319ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.470s	33.722us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.220s	499.195us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.220s	499.195us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.290s	39.708us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	45.165us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	127.136us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	95.189us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.290s	39.708us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	45.165us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	127.136us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	95.189us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
		lc_ctrl_tl_intg_err	4.490s	117.994us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.490s	117.994us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.830s	1.338ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.920s	1.261ms	50	50	100.00
		lc_ctrl_sec_cm	38.540s	221.578us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.480s	5.034ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.920s	102.738us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.760s	17.148ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.140s	1.004ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.140s	1.004ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.060s	4.607ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.320s	3.653ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.320s	3.653ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.972h	139.303ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.99	95.95	93.40	97.67	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 14 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.43229463039944594667543140396060953772521396801166283371452083225127289000756
      Line 24150, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22369513781 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22369513781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.102408876314905144574133990856566437663929734053879386273045672433978656139807
      Line 10213, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7180926737 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7180926737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.46598446628442964039040836590987978576974755256582938243066709496105741558043
      Line 25920, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 10.lc_ctrl_stress_all_with_rand_reset.33477920945077701188395165139727442643443442064457207586645686391417369724328
      Line 28859, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 2 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 14.lc_ctrl_jtag_errors.84229632472768160357494792990027993169011861731814593252406565363906326854600
      Line 2427, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 3207410650 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3207410650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_errors has 1 failures.

    • 41.lc_ctrl_errors.48860447500308038989075516380356017976757026144894840380527363866560428412364
      Line 2872, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 1700325560 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1700325560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.53987879209352679681845401439205316257163482067844544241255116961520189356812
      Line 34495, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67919282476 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked2
        UVM_INFO @ 67919282476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.13675225038555713764312166255987715641353865672275301503789425084722864509998
      Line 22694, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 59379318097 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 59379318097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.3418870840233290811293360819080131711911623353604770393248987168571645796286
      Line 1776, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1475479311 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked7
        UVM_INFO @ 1475479311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.21867573348537052469545592144203284008715843031594134091520977899503370688448
      Line 23517, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 213082057619 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 213082057619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.31_09.05.46
• 2024.07.30_09.23.26
• 2024.07.29_07.48.21
• 2024.07.28_10.46.59
• 2024.07.27_09.38.49
• 2024.07.26_09.02.00
• 2024.07.25_08.32.56