LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.550s	1.891ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	138.240us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	51.750us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.280s	96.431us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.400s	18.164us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.180s	111.275us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	51.750us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	18.164us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.220s	302.758us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.210s	349.826us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	14.786us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.570s	515.518us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.350s	1.154ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_prog_failure	5.570s	515.518us	50	50	100.00
		lc_ctrl_errors	24.350s	1.154ms	50	50	100.00
		lc_ctrl_security_escalation	15.910s	510.064us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.595m	2.698ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.710s	2.655ms	20	20	100.00
		lc_ctrl_jtag_errors	2.289m	5.095ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	23.250s	1.826ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.880s	6.471ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.710s	2.655ms	20	20	100.00
		lc_ctrl_jtag_errors	2.289m	5.095ms	20	20	100.00
		lc_ctrl_jtag_access	27.990s	5.053ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.940s	1.384ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.350s	313.272us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.350s	164.142us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.090s	17.353ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.770s	4.632ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.270s	50.435us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.840s	835.551us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.960s	167.067us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	8.010s	1.208ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.490s	23.703us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.017m	128.847ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.600s	90.491us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.070s	254.696us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.070s	254.696us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	138.240us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	51.750us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	18.164us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.170s	53.298us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	138.240us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	51.750us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	18.164us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.170s	53.298us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
		lc_ctrl_tl_intg_err	4.550s	2.252ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.550s	2.252ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.210s	349.826us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.380s	1.340ms	50	50	100.00
		lc_ctrl_sec_cm	39.340s	845.875us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.910s	510.064us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.220s	302.758us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.880s	6.471ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	32.830s	941.216us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	32.830s	941.216us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.060s	567.701us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.120s	3.452ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.120s	3.452ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.031h	63.177ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1009	1030	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.84	97.99	95.86	93.40	97.67	98.55	98.51	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 15 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.43211289381799999118459503702919060579542535266412750154254624017952107571701
      Line 3826, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9497819376 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9497819376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.45778764755089622044770465195854154754291772378622305360869895456998228522189
      Line 44765, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30414879303 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 30414879303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 31.lc_ctrl_stress_all.61104960916107850444342788629291431457309912199837620921356311250184580109044
      Line 2873, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3015104214 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3015104214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.lc_ctrl_stress_all.91589953022509586511935129331400692506437165002915879497969831119013883437574
      Line 2062, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3535643241 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3535643241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.114149721636583108359444537644883516058093129880988805766832608735274435932146
      Line 11985, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37759050202 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 37759050202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.105675232742491868070422075266991963379230021645536796706757266312298549508238
      Line 35077, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.12814895312827433179575765076438948931586013703010061104611597913408027371563
      Line 54929, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 90157371801 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 90157371801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.95262774097709008319770386552734849587113951584861264390043048957905930858928
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:f52ce0fb-12bc-4e0d-8917-7959fe5bdf30
      

Past Results

• Latest
• 2024.08.01_09.36.30
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