LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.220s	270.429us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	164.293us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.080s	14.250us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.880s	311.130us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.290s	49.533us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.920s	31.909us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.080s	14.250us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	49.533us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.970s	111.673us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.960s	475.831us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	13.822us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.320s	150.783us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	17.400s	398.381us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_prog_failure	4.320s	150.783us	50	50	100.00
		lc_ctrl_errors	17.400s	398.381us	50	50	100.00
		lc_ctrl_security_escalation	14.460s	1.179ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.137m	4.382ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.120s	3.778ms	20	20	100.00
		lc_ctrl_jtag_errors	2.092m	8.777ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.830s	2.428ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.620s	4.217ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.120s	3.778ms	20	20	100.00
		lc_ctrl_jtag_errors	2.092m	8.777ms	20	20	100.00
		lc_ctrl_jtag_access	21.790s	1.841ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.570s	5.132ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.460s	238.463us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.610s	407.495us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	41.840s	4.655ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	29.810s	5.642ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	45.392us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.910s	198.260us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.200s	445.618us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.000s	3.196ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.200s	32.963us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.614m	130.347ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	57.056us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.310s	97.864us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.310s	97.864us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	164.293us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	14.250us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	49.533us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	215.745us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	164.293us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	14.250us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	49.533us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	215.745us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
		lc_ctrl_tl_intg_err	4.140s	117.963us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.140s	117.963us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.960s	475.831us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.060s	394.680us	50	50	100.00
		lc_ctrl_sec_cm	35.040s	214.084us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.460s	1.179ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.970s	111.673us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.620s	4.217ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	30.220s	3.287ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	30.220s	3.287ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.750s	1.032ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.530s	372.694us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.530s	372.694us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	54.858m	85.581ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1009	1030	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.99	96.04	93.40	100.00	98.55	98.51	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 17 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.14355207058179423621801471274779235157875607806510912124359348897523768364410
    Line 34046, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59116402872 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 59116402872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.lc_ctrl_stress_all_with_rand_reset.19623713849971891847296663575059377636286555587472887740173627162232825776430
    Line 16171, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38528795050 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38528795050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.90583629499483066662880040024999707844707879011041756670792709970840068003698
    Line 469, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  82378525 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  82378525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:762) [lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.lc_ctrl_stress_all_with_rand_reset.72022133215905155012123845875443987427420966977025147867369636936268765200421
    Line 12487, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 456843158578 ps: (lc_ctrl_errors_vseq.sv:762) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 456843158578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.lc_ctrl_stress_all_with_rand_reset.55573525113044958229359133935332727642446460548444258225892526746462179791769
    Line 10985, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7988641062 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 7988641062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.lc_ctrl_stress_all_with_rand_reset.56916371995883943980092178926269847500304683569436598359723560557133600899601
    Line 40444, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39613075086 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 39613075086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`