LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.150s	100.816us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	13.804us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.080s	58.075us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.900s	123.133us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.850s	78.126us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.150s	30.202us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.080s	58.075us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	78.126us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.060s	66.598us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.500s	1.389ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	10.974us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.520s	274.439us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.310s	1.861ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_prog_failure	5.520s	274.439us	50	50	100.00
		lc_ctrl_errors	23.310s	1.861ms	50	50	100.00
		lc_ctrl_security_escalation	15.130s	395.882us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.266m	11.490ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.500s	2.954ms	20	20	100.00
		lc_ctrl_jtag_errors	1.797m	7.852ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.060s	10.209ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.230s	1.888ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.500s	2.954ms	20	20	100.00
		lc_ctrl_jtag_errors	1.797m	7.852ms	20	20	100.00
		lc_ctrl_jtag_access	26.000s	4.527ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.050s	10.601ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.470s	121.629us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.310s	110.711us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	52.370s	2.618ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.420s	1.440ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.500s	33.631us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.700s	240.487us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.880s	217.676us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.101m	2.971ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.320s	37.750us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.176m	66.551ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.400s	57.909us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.230s	134.914us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.230s	134.914us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	13.804us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	58.075us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	78.126us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	47.333us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	13.804us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	58.075us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	78.126us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	47.333us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
		lc_ctrl_tl_intg_err	4.710s	308.854us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.710s	308.854us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.500s	1.389ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.290s	1.389ms	50	50	100.00
		lc_ctrl_sec_cm	40.170s	218.460us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.130s	395.882us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.060s	66.598us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.230s	1.888ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.500s	2.830ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.500s	2.830ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.080s	1.286ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.970s	3.201ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.970s	3.201ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	37.355m	57.685ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1011	1030	98.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.99	95.68	93.40	97.67	98.55	98.51	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 16 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.54763775288847704765161302609931608107260292436028591839700997900741185215957
    Line 25782, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28006838774 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28006838774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.54707525751906335988015430593569561425269745199699868796110305596728419030159
    Line 7184, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15045678470 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15045678470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 8.lc_ctrl_stress_all_with_rand_reset.104812314972245494052444214186864737936014802430208367322338265188761811255088
    Line 22580, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16763366229 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16763366229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.lc_ctrl_stress_all_with_rand_reset.38927315856828321038255129442073206031231119451077111850469488990843545887774
    Line 20513, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51269006762 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 51269006762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.lc_ctrl_stress_all_with_rand_reset.60823615082856004513439227027813037155787890641630672504263511768379792013366
    Line 24789, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`