LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.580s	1.330ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	129.873us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	19.760us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.900s	101.913us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.660s	125.838us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.830s	44.345us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	19.760us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	125.838us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.410s	84.243us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.960s	802.161us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	12.481us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.180s	445.531us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.010s	2.280ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_prog_failure	5.180s	445.531us	50	50	100.00
		lc_ctrl_errors	22.010s	2.280ms	50	50	100.00
		lc_ctrl_security_escalation	17.080s	1.752ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.094m	15.048ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.030s	1.159ms	20	20	100.00
		lc_ctrl_jtag_errors	1.817m	17.831ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.690s	926.680us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.260s	1.125ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.030s	1.159ms	20	20	100.00
		lc_ctrl_jtag_errors	1.817m	17.831ms	20	20	100.00
		lc_ctrl_jtag_access	30.340s	2.706ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.480s	1.519ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.630s	178.853us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.750s	149.124us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.760s	4.015ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.520s	802.948us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.800s	33.870us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.170s	175.536us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.670s	802.968us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	35.940s	7.022ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.160s	15.013us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.313m	138.593ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.670s	48.583us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.640s	195.342us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.640s	195.342us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	129.873us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	19.760us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	125.838us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	704.030us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	129.873us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	19.760us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	125.838us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	704.030us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
		lc_ctrl_tl_intg_err	4.220s	469.384us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.220s	469.384us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.960s	802.161us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.900s	1.077ms	50	50	100.00
		lc_ctrl_sec_cm	36.620s	939.107us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.080s	1.752ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.410s	84.243us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.260s	1.125ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.340s	736.925us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.340s	736.925us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.060s	1.128ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.700s	1.125ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.700s	1.125ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.103h	26.165ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.86	97.99	95.77	93.40	97.67	98.55	98.51	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 20 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.65347271720719716081761187968420935524341233736538769839928957332238091494880
    Line 11780, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32783331114 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32783331114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.82371462603518153201371548329123957866473740987091754754492003030268470826491
    Line 17489, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91642369995 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 91642369995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.94582565147404857703305546984178626340561504442655664973801854630157720006458
    Line 22821, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22371969828 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 22371969828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 6.lc_ctrl_stress_all_with_rand_reset.49863119827726709417915601133075827725807915170369292240140671495049552653786
    Line 17285, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21192484135 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 21192484135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.lc_ctrl_stress_all_with_rand_reset.2443036803117900909862237822011840542457879022070028811352159673981937516325
    Line 19431, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53674784492 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 53674784492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.lc_ctrl_stress_all_with_rand_reset.72366879413385897951842547424985482990241028038142019026709230818218043214635
    Line 55341, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`