LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.210s	237.717us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.100s	27.799us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.270s	20.135us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.110s	346.933us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	24.496us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.910s	56.170us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.270s	20.135us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	24.496us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.610s	660.897us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.140s	779.689us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	22.108us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.080s	169.343us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.750s	8.081ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_prog_failure	7.080s	169.343us	50	50	100.00
		lc_ctrl_errors	26.750s	8.081ms	50	50	100.00
		lc_ctrl_security_escalation	16.400s	1.056ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.526m	2.804ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.540s	2.473ms	20	20	100.00
		lc_ctrl_jtag_errors	2.324m	37.908ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.280s	2.346ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	38.660s	5.739ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.540s	2.473ms	20	20	100.00
		lc_ctrl_jtag_errors	2.324m	37.908ms	20	20	100.00
		lc_ctrl_jtag_access	30.830s	7.237ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.320s	1.394ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.080s	1.162ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.480s	455.079us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	40.050s	1.797ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.830s	869.627us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.630s	64.164us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.150s	178.385us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.460s	293.030us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.790s	5.633ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	14.166us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.065m	24.947ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.450s	32.130us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.350s	538.030us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.350s	538.030us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.100s	27.799us	5	5	100.00
		lc_ctrl_csr_rw	1.270s	20.135us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	24.496us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	47.992us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.100s	27.799us	5	5	100.00
		lc_ctrl_csr_rw	1.270s	20.135us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	24.496us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	47.992us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.230s	300.680us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.230s	300.680us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.140s	779.689us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.460s	2.546ms	50	50	100.00
		lc_ctrl_sec_cm	38.730s	1.299ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.400s	1.056ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.610s	660.897us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	38.660s	5.739ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.280s	3.611ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.280s	3.611ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.260s	5.549ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.990s	932.717us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.990s	932.717us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	41.542m	274.692ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1008	1030	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	97.99	95.50	93.40	100.00	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 16 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.79793972055192395126318649493407085852393548152028331503381809997470064275696
      Line 19568, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28699216616 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28699216616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.105201724716913037756895653892710764173679623757873066632672205300935310421098
      Line 20409, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16109201372 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16109201372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.83657624286638309247386463897538039639494834515763461774846870917132401725662
      Line 24996, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52713007418 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 52713007418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.lc_ctrl_stress_all_with_rand_reset.57101048876715987202772279677818924628739046239702552911047121177766810460502
      Line 18929, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 64440697823 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 64440697823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 10.lc_ctrl_stress_all_with_rand_reset.38907103311844379459353796371930495528130382241405267363047742277807713269452
      Line 71208, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 180018671608 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 180018671608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.lc_ctrl_stress_all_with_rand_reset.47304030281178777103507740608103379344899243045226225184459703179423224891216
      Line 27850, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28345277295 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 28345277295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:755) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.99872463780192935607563724620968002709361872914521736417644148078067298952301
      Line 24086, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19047982083 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 19047982083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.05_10.56.58
• 2024.08.04_06.45.09
• 2024.08.03_08.56.09
• 2024.08.02_08.10.41
• 2024.08.01_09.36.30
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