LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.980s	788.507us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.210s	43.472us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	19.191us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.760s	160.071us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.420s	21.946us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.090s	31.263us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	19.191us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	21.946us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.130s	621.561us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	28.040s	3.137ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.050s	13.705us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.030s	701.690us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.540s	2.704ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_prog_failure	5.030s	701.690us	50	50	100.00
		lc_ctrl_errors	25.540s	2.704ms	50	50	100.00
		lc_ctrl_security_escalation	19.070s	3.458ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.146m	59.431ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.630s	2.949ms	20	20	100.00
		lc_ctrl_jtag_errors	1.185m	2.524ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.590s	565.717us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.690s	840.094us	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.630s	2.949ms	20	20	100.00
		lc_ctrl_jtag_errors	1.185m	2.524ms	19	20	95.00
		lc_ctrl_jtag_access	28.960s	5.127ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.000s	4.759ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.820s	592.758us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.020s	57.805us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	40.210s	1.922ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.360s	3.115ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.580s	24.178us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.520s	1.006ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.150s	58.788us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	9.900s	1.135ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.440s	23.755us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.734m	36.861ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.320s	45.630us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.940s	121.359us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.940s	121.359us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.210s	43.472us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.191us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	21.946us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.130s	46.481us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.210s	43.472us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.191us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	21.946us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.130s	46.481us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
		lc_ctrl_tl_intg_err	4.340s	216.026us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.340s	216.026us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	28.040s	3.137ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.140s	520.526us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	884.544us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.070s	3.458ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.130s	621.561us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.690s	840.094us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.020s	3.038ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.020s	3.038ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.330s	1.404ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.680s	714.705us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.680s	714.705us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.663h	160.746ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.79	97.99	95.32	93.40	97.67	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.92322903068810834151586988014198228987742987793943331886655963937849873238936
      Line 21608, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70453859260 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 70453859260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.83072016456396921321264104247213099188984174927159630372421046863314701727315
      Line 15163, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16193615162 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16193615162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 0.lc_ctrl_stress_all.8153488108623707560919503942979453808015509456795394786474816861388874386306
      Line 2078, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 853651726 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 853651726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 1.lc_ctrl_jtag_errors.74440229838776810563265185888622949422773262833609261551458772783010299656735
      Line 2217, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 2275078450 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2275078450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.70758282574579470485457208996983172627876088223126965679556000738641481282385
      Line 52273, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.19009909605561365444524395516281090950675150539766789035689820951829773494522
      Line 43996, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 183118471974 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 183118471974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.82538322596275257653927193493716784665151624097398667780894453026101052923008
      Line 20594, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 147084624130 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 147084624130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.06_09.28.36
• 2024.08.05_10.56.58
• 2024.08.04_06.45.09
• 2024.08.03_08.56.09
• 2024.08.02_08.10.41
• 2024.08.01_09.36.30
• 2024.07.31_09.05.46