LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.830s	214.505us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	15.050us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	16.839us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.180s	375.808us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.410s	19.703us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.970s	47.160us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	16.839us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	19.703us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.500s	204.316us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.760s	1.375ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	12.344us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.430s	839.541us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.790s	824.308us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_prog_failure	4.430s	839.541us	50	50	100.00
		lc_ctrl_errors	23.790s	824.308us	50	50	100.00
		lc_ctrl_security_escalation	14.730s	669.576us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.494m	21.785ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.530s	999.241us	20	20	100.00
		lc_ctrl_jtag_errors	1.934m	10.152ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.920s	2.372ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.970s	4.425ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.530s	999.241us	20	20	100.00
		lc_ctrl_jtag_errors	1.934m	10.152ms	20	20	100.00
		lc_ctrl_jtag_access	16.400s	5.027ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.920s	1.446ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.140s	290.133us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.240s	126.582us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	37.950s	1.800ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.680s	1.478ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	139.152us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.840s	269.146us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.190s	61.235us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.260s	851.422us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	92.168us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.037m	15.865ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.420s	30.240us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.640s	153.911us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.640s	153.911us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	15.050us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	16.839us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	19.703us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	43.746us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	15.050us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	16.839us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	19.703us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	43.746us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
		lc_ctrl_tl_intg_err	3.990s	190.692us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.990s	190.692us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.760s	1.375ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.220s	332.891us	50	50	100.00
		lc_ctrl_sec_cm	38.210s	813.967us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.730s	669.576us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.500s	204.316us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.970s	4.425ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.140s	3.471ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.140s	3.471ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.550s	1.973ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.870s	2.024ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.870s	2.024ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.689h	169.888ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.99	96.13	93.40	100.00	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.35806867042564186367093768740103362624809671841218146587672811420545214136555
      Line 343, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1054447043 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1054447043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.18555276876379347674574519641422616374569756826114456809689508861266464225476
      Line 18016, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14470610242 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14470610242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.109641322621363139069225851638292535403061563223475019714649831629811151408799
      Line 73588, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 20.lc_ctrl_stress_all_with_rand_reset.110633962081909789324803879207815732081497150943363043925915877633554540658453
      Line 53332, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 2 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.16592088685915476596089234718444354456870677602894639445947587382938550779432
      Line 43017, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 77796253523 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 77796253523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 44.lc_ctrl_stress_all_with_rand_reset.66097774897713322044987856955311736294932213516926374355305173583993825336738
      Line 44297, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75824263984 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 75824263984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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