LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.960s	136.941us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	15.642us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	23.765us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.750s	134.131us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.400s	67.298us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.130s	30.539us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	23.765us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	67.298us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.070s	230.834us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.610s	363.719us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.714us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.890s	286.430us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.600s	3.676ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_prog_failure	5.890s	286.430us	50	50	100.00
		lc_ctrl_errors	21.600s	3.676ms	50	50	100.00
		lc_ctrl_security_escalation	15.900s	770.056us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.968m	14.443ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	30.070s	1.077ms	20	20	100.00
		lc_ctrl_jtag_errors	2.326m	21.391ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.340s	780.667us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	40.120s	2.595ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	30.070s	1.077ms	20	20	100.00
		lc_ctrl_jtag_errors	2.326m	21.391ms	20	20	100.00
		lc_ctrl_jtag_access	23.050s	5.607ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	29.980s	4.050ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.420s	1.319ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.310s	663.868us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	46.200s	3.306ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.490s	957.825us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.810s	80.841us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.110s	457.655us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.100s	127.310us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.100s	2.524ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.240s	31.162us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	17.324m	133.637ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.460s	119.430us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.300s	538.470us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.300s	538.470us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	15.642us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	23.765us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	67.298us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	42.209us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	15.642us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	23.765us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	67.298us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	42.209us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
		lc_ctrl_tl_intg_err	4.260s	119.441us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.260s	119.441us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.610s	363.719us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.280s	800.140us	50	50	100.00
		lc_ctrl_sec_cm	24.550s	123.972us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.900s	770.056us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.070s	230.834us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	40.120s	2.595ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.180s	2.301ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.180s	2.301ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.630s	1.264ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.180s	3.353ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.180s	3.353ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.829h	42.644ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.15	97.99	95.68	93.40	100.00	98.55	98.51	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.10194608148698522060212703285787232943190165171317871426707295623589977158863
      Line 3788, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3019853908 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3019853908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.61691583239797458729906419602922029037209227008085343210018860396537235851210
      Line 33500, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46931566813 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 46931566813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.27959325262958324420054969759004404113182464519878080443511199817868659673025
      Line 41355, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32704570702 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 32704570702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_stress_all_with_rand_reset.10750847792589226788570723250750052786156161289104738477717015974287348728461
      Line 44383, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 117401271510 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 117401271510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

Past Results

• Latest
• 2024.08.08_09.03.52
• 2024.08.07_08.56.58
• 2024.08.06_09.28.36
• 2024.08.05_10.56.58
• 2024.08.04_06.45.09
• 2024.08.03_08.56.09
• 2024.08.02_08.10.41