LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.870s	106.024us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.040s	17.622us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	16.979us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.950s	399.954us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.750s	38.840us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.810s	45.397us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	16.979us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	38.840us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.350s	84.327us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.130s	323.162us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	11.654us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.800s	209.179us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.370s	816.233us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_prog_failure	4.800s	209.179us	50	50	100.00
		lc_ctrl_errors	19.370s	816.233us	50	50	100.00
		lc_ctrl_security_escalation	16.440s	511.483us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.370m	3.564ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.920s	4.414ms	20	20	100.00
		lc_ctrl_jtag_errors	1.688m	3.728ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.430s	6.294ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.050s	2.843ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.920s	4.414ms	20	20	100.00
		lc_ctrl_jtag_errors	1.688m	3.728ms	20	20	100.00
		lc_ctrl_jtag_access	18.660s	3.400ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.390s	2.341ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.900s	781.417us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.550s	531.380us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	42.570s	7.680ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.540s	2.474ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.890s	84.020us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.630s	296.980us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.280s	74.815us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	23.460s	4.595ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.320s	61.763us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.857m	111.988ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.810s	56.304us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.530s	114.005us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.530s	114.005us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.040s	17.622us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.979us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	38.840us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	55.354us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.040s	17.622us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.979us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	38.840us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	55.354us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
		lc_ctrl_tl_intg_err	4.240s	233.296us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.240s	233.296us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.130s	323.162us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.010s	1.791ms	50	50	100.00
		lc_ctrl_sec_cm	39.740s	870.679us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.440s	511.483us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.350s	84.327us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.050s	2.843ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.620s	1.198ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.620s	1.198ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.840s	497.472us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.710s	2.082ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.710s	2.082ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	30.401m	89.499ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.90	97.99	95.86	93.40	97.67	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 15 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.73312187149148516651345180315915816743046836247184286506016760570225731979304
      Line 26622, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19549951252 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19549951252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.78292559559647727354479996019651026259971125299862284263769347484696283127721
      Line 6887, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6510752763 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6510752763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.88146397662551435840622607628735986661902335906743871918586354828857851451587
      Line 37769, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 98903358877 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 98903358877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.lc_ctrl_stress_all_with_rand_reset.37389768429003980981119034824066943614289240428401203965186614988762427638279
      Line 30853, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11591857291 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11591857291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.101379889316433243065374610575264712312399650411108530360115372208241718157540
      Line 14739, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10957342113 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 10957342113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.lc_ctrl_stress_all_with_rand_reset.105085686230444755865840305087430521234615670522104229650094089374672994742175
      Line 26596, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35999600196 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 35999600196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.64071720213776010689215153842365159088950285593078640295716779087550179589136
      Line 479, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 919597498 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 919597498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.14112989147032676448300262652780787184405463760140403753395798702250022480729
      Line 27611, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

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