LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.240s	1.025ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	14.046us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	31.676us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.060s	971.688us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.620s	162.420us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.410s	32.422us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	31.676us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	162.420us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.840s	429.748us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.680s	314.452us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	12.166us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.520s	343.044us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.560s	4.891ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_prog_failure	5.520s	343.044us	50	50	100.00
		lc_ctrl_errors	23.560s	4.891ms	50	50	100.00
		lc_ctrl_security_escalation	16.080s	1.903ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.747m	2.839ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.740s	1.720ms	20	20	100.00
		lc_ctrl_jtag_errors	1.853m	15.831ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.530s	614.455us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.640s	853.671us	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.740s	1.720ms	20	20	100.00
		lc_ctrl_jtag_errors	1.853m	15.831ms	20	20	100.00
		lc_ctrl_jtag_access	16.120s	2.432ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.330s	21.066ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.040s	3.298ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.440s	1.073ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.680s	12.079ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.290s	452.020us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	38.098us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.280s	191.798us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.710s	93.633us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	38.790s	2.290ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	68.673us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.267m	19.491ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.580s	49.267us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.050s	130.796us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.050s	130.796us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	14.046us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	31.676us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	162.420us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	42.999us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	14.046us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	31.676us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	162.420us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	42.999us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
		lc_ctrl_tl_intg_err	6.220s	237.487us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.220s	237.487us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.680s	314.452us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.310s	1.183ms	50	50	100.00
		lc_ctrl_sec_cm	42.920s	298.133us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.080s	1.903ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.840s	429.748us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.640s	853.671us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.310s	887.659us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.310s	887.659us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.260s	3.057ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.700s	5.302ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.700s	5.302ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	54.678m	39.391ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.99	95.86	93.40	97.67	98.55	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.68497754131103930403620338163346841378332756083682834357650280528200166727827
      Line 391, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3614721232 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3614721232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.22135417118033133723730335128280121069092731465012137488461233486038023214687
      Line 18280, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 76782278961 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 76782278961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.72225332484912237056649023911904161108551210804366284457148082239719249086442
      Line 48859, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 5.lc_ctrl_stress_all_with_rand_reset.86041672623537297553442889017214720882630102543002024153505740416235672089573
      Line 31863, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.24209664087518427103892652752114682358825100945908897363446415542550830299425
      Line 20299, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40772713705 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 40772713705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 42.lc_ctrl_stress_all_with_rand_reset.21338029125320937857198924995451235271746992472264554218913869158921607908981
      Line 26480, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10967034291 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 10967034291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.10_08.20.05
• 2024.08.09_07.51.29
• 2024.08.08_09.03.52
• 2024.08.07_08.56.58
• 2024.08.06_09.28.36
• 2024.08.05_10.56.58
• 2024.08.04_06.45.09