LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.700s	229.610us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	17.486us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.040s	15.380us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.050s	1.445ms	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	46.405us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.320s	33.693us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.040s	15.380us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	46.405us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.120s	543.399us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.040s	1.093ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	22.179us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.780s	426.322us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.700s	8.203ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_prog_failure	4.780s	426.322us	50	50	100.00
		lc_ctrl_errors	22.700s	8.203ms	50	50	100.00
		lc_ctrl_security_escalation	16.420s	5.162ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.578m	15.006ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.930s	626.591us	20	20	100.00
		lc_ctrl_jtag_errors	1.505m	13.697ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.560s	3.151ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.940s	1.638ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.930s	626.591us	20	20	100.00
		lc_ctrl_jtag_errors	1.505m	13.697ms	20	20	100.00
		lc_ctrl_jtag_access	27.950s	4.688ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.390s	2.646ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.120s	505.062us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.680s	96.159us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.380s	1.519ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.790s	3.134ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.990s	228.421us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.630s	428.553us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.470s	291.865us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.840s	5.596ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	20.480us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.821m	17.385ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	52.752us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.070s	553.192us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.070s	553.192us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	17.486us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	15.380us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	46.405us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	184.025us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	17.486us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	15.380us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	46.405us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	184.025us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
		lc_ctrl_tl_intg_err	8.140s	1.379ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	8.140s	1.379ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.040s	1.093ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.760s	720.898us	50	50	100.00
		lc_ctrl_sec_cm	25.750s	578.803us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.420s	5.162ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.120s	543.399us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.940s	1.638ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.190s	2.642ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.190s	2.642ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.190s	1.546ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.300s	1.919ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.300s	1.919ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	37.535m	60.869ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.99	95.68	93.40	97.67	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.55211358323975679087037945902431322756464442692084523021252600001273788467618
      Line 13272, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19247579944 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19247579944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.27925147136531501537082738590882928718671076205398506756458744732490261720321
      Line 12506, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 154645262464 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 154645262464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.17675563827141618545272087924142495270341218099841034240831009912178458397533
      Line 25933, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 174359194624 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 174359194624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.lc_ctrl_stress_all_with_rand_reset.113965904503900908183134460070022457719040570105305523357793112333766081398531
      Line 34120, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63056571315 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 63056571315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.26284999626254860867007924199946898407261287898246895551538663500991918600556
      Line 39579, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 37.lc_ctrl_stress_all_with_rand_reset.64384773867267875282093947970552946845190169434007222953035680777536855092873
      Line 46770, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 44.lc_ctrl_stress_all_with_rand_reset.87408091197398919349712738836738320516340241594678701854972694297494149085785
      Line 38126, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24927812865 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 24927812865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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