LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.900s	566.418us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.150s	13.258us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.190s	19.795us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.850s	259.402us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.030s	38.309us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.080s	26.706us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.190s	19.795us	20	20	100.00
		lc_ctrl_csr_aliasing	2.030s	38.309us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.080s	303.831us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.980s	518.998us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.040s	13.265us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.920s	1.014ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.250s	504.252us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_prog_failure	6.920s	1.014ms	50	50	100.00
		lc_ctrl_errors	22.250s	504.252us	50	50	100.00
		lc_ctrl_security_escalation	18.450s	2.608ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.762m	3.086ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.380s	1.306ms	20	20	100.00
		lc_ctrl_jtag_errors	1.745m	3.922ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.230s	1.660ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	38.900s	1.201ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.380s	1.306ms	20	20	100.00
		lc_ctrl_jtag_errors	1.745m	3.922ms	20	20	100.00
		lc_ctrl_jtag_access	19.380s	1.023ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.390s	1.290ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.180s	96.036us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.800s	138.033us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	41.560s	1.781ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.280s	444.403us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.020s	333.235us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.850s	304.765us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.840s	97.141us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.440s	3.849ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.600s	20.330us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.252m	25.548ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.410s	171.968us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.550s	216.176us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.550s	216.176us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.150s	13.258us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	19.795us	20	20	100.00
		lc_ctrl_csr_aliasing	2.030s	38.309us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	44.804us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.150s	13.258us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	19.795us	20	20	100.00
		lc_ctrl_csr_aliasing	2.030s	38.309us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	44.804us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.530s	119.340us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.530s	119.340us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.980s	518.998us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.730s	318.580us	50	50	100.00
		lc_ctrl_sec_cm	42.680s	2.182ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.450s	2.608ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.080s	303.831us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	38.900s	1.201ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.780s	16.686ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.780s	16.686ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.980s	977.029us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.390s	679.683us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.390s	679.683us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.663m	4.735ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.99	96.04	93.40	97.67	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:848) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.55053175099631512671551333046976817077239915206484286820284573643421991802516
      Line 10299, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3274212204 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3274212204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.58179510806447409804766438476167755361637587301784006305026163365228673814145
      Line 6001, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10675926197 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10675926197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.70971484947992197855378541745203888108200754838953589563022953868988929705810
      Line 4407, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2725371146 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2725371146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.lc_ctrl_stress_all_with_rand_reset.47323339613586388628795489542522463790853703949919944315862949230449091826865
      Line 4148, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2351893565 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2351893565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 14.lc_ctrl_stress_all.91881141948774067945130019535248399770977936419838080871849578501065793904025
      Line 9066, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3903554719 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3903554719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.74305527383371550546222225425121067864808015336494297683579852304675009235110
      Line 5253, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1750365103 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 1750365103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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