LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.850s	150.450us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	19.877us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.000s	12.769us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.930s	551.842us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	85.899us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.450s	32.545us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.000s	12.769us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	85.899us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.900s	65.327us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.940s	453.779us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	12.475us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.800s	335.648us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.500s	3.852ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_prog_failure	4.800s	335.648us	50	50	100.00
		lc_ctrl_errors	24.500s	3.852ms	50	50	100.00
		lc_ctrl_security_escalation	15.330s	8.426ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.746m	13.160ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.800s	1.042ms	20	20	100.00
		lc_ctrl_jtag_errors	1.476m	12.462ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.160s	965.758us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.400s	6.387ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.800s	1.042ms	20	20	100.00
		lc_ctrl_jtag_errors	1.476m	12.462ms	20	20	100.00
		lc_ctrl_jtag_access	22.880s	968.648us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.750s	4.419ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.340s	229.707us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.960s	2.061ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	33.900s	6.027ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	29.720s	3.630ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.040s	214.332us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.900s	240.933us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.300s	297.707us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.550s	5.297ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.680s	44.319us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.700m	292.763ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.340s	27.130us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.980s	141.249us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.980s	141.249us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	19.877us	5	5	100.00
		lc_ctrl_csr_rw	1.000s	12.769us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	85.899us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	460.662us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	19.877us	5	5	100.00
		lc_ctrl_csr_rw	1.000s	12.769us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	85.899us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	460.662us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
		lc_ctrl_tl_intg_err	4.020s	452.154us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.020s	452.154us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.940s	453.779us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.740s	367.892us	50	50	100.00
		lc_ctrl_sec_cm	24.670s	410.618us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.330s	8.426ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.900s	65.327us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.400s	6.387ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.510s	1.528ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.510s	1.528ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.810s	1.245ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.880s	1.707ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.880s	1.707ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.596m	5.924ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.99	95.59	93.40	97.67	98.55	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.31209958156816328996674941475531397754486458616719530068115229866855865159412
      Line 2056, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20673740368 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20673740368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.14433994725402949396269743547838619433010987967427903597279976855545857318779
      Line 5769, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1863287778 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1863287778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.48755582831580118439174452290357953635778565667450878575758266081634149332015
      Line 5372, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3776437365 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 3776437365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.8654305770114278840891222677267621774434754583554216765014167149595986244951
      Line 8118, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3816373746 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 3816373746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
  • Test lc_ctrl_stress_all has 1 failures.

    • 11.lc_ctrl_stress_all.106984104552936523526063401975380938394445688845459346906665472825691517546964
      Line 6544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3607178735 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3607178735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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